Design of an Intelligent NPID Controller Based on Genetic Algorithm for Disturbance Rejection in Single Integrating Process with Time Delay

Abstract

The integrating process with time delay (IPTD) is a fundamentally unstable open-loop system due to poles at the origin of the transfer function, and designing controllers with satisfactory control performance is very difficult because of the associated time delay, which is a nonlinear element. Therefore, this study focuses on the design of an intelligent proportional-integral-derivative (PID) controller to improve the regulatory response performance to disturbance in an IPTD, and addresses problems related to optimally tuning each parameter of the controller with a real coded genetic algorithm (RCGA). Each gain of the nonlinear PID (NPID) controller consists of a product of the gains of the linear PID controller and a simple nonlinear function. Each of these nonlinear functions changes the gains in the controller to on line by nonlinearly scaling the error signal. A lead-lag compensator or first-order filter is also added to the controller to mitigate noise, which is a disadvantage of ideal derivative action. The parameters in the controller are optimally tuned by minimizing the integral of time-weighted absolute error (ITAE) using a RCGA. The proposed method is compared with three other methods through simulation to verify its effectiveness.

Optimal integral–proportional derivative controller design for input load disturbance rejection of time delay integrating processes

“…Verma and Padhy 20 derived proportional–integral (PI)/PID tuning rules using two new objective functions to control PIPDT and stable/unstable first order plus dead time processes. So 21 designed an intelligent nonlinear PID controller for improving input load disturbance rejection performance of PIPDT and IFOPDT processes.…”

Tuning of a control compensator from the first generation with comparison with compensators from the second compensator generation

“…They used simulation results derived using the cadence IC design suite and the design kit of the Austria Mikro Systeme to evaluate the performance of the presented designs [18]. So (2021) focused on the design of an intelligent PID (proportional -integral-derivative) controller to improve the regularity response performance to disturbance in an IPID. He used a lead/lag compensatorof first order filter added to the controller to mitigate the noise.…”

“…He used a lead/lag compensatorof first order filter added to the controller to mitigate the noise. He tuned the controller parameters using the ITAE error functions using the real coded genetic algorithm and compared three other methods [19].…”