Design of arbitrated I2C protocol with DO-254 compliance

Bharath, K. B.; Kumaraswamy, K V; Swamy, Roopa K

doi:10.1109/icett.2016.7873672

Cited by 8 publications

(2 citation statements)

References 2 publications

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“…Most of the existing two wire I 2 C or SCCB interface architecture use the FSM model [22] or interdependent counters [23] to perform serialization which increases the design complexity and hardware requirements.…”

Section: Proposed Architecturementioning

confidence: 99%

“…Similarly, the signal id is used to define the operating mode of the camera registers (i.e., read or write) by considering a specific value depending upon corresponding camera datasheet [12,13]. Most of the existing two wire I 2 C or SCCB interface architecture use the FSM model [22] or interdependent counters [23] to perform serialization which increases the design complexity and hardware requirements.…”

Section: Modified Sccb Format Generationmentioning

confidence: 99%

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FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing

Sarkar

Bhairannawar

Raja

2021

IET Circuits, Devices & Syst

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In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an efficient FPGA-based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time efficiently. The flexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Conversion has been modified to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Proposed Architecturementioning

confidence: 99%

Section: Modified Sccb Format Generationmentioning

confidence: 99%