Design of code error detector based on FPGA

Abstract

With the development of social productivity and the improvement of people's living standard, the development of modern computer technology is more and more fast. In the communication system, the code error detector is the important equipment to detect reliability of communication system, and the traditional code error detector is based on collaborative work of CPLD and CPU[1], not only is the structure complex, expensive, but it is inconvenient to carry. Code error detector based on FPGA, using FPGA to complete the integration of design of control and test module, to improve the scalability and integration of the system. This paper is based on principle of M sequence generation and code error detection, using the VHDL hardware description language, to realize the design of a simple bit by bit comparison code error detector and the simulation of each function module.