Deleting the average class of constant false alarm rate monitoring (CMLD-CFAR) ,which bases on an average constant false alarm rate monitoring(CA-CFAR) ,can not only overcome the ML type detector under the background of multiple targets detection problem of poor performance, but also address the traditional OS type detector false alarm rate problem of the great losses[1].This paper regards the FPGA as a platform.Firstly use MATLAB simulation produces radar echo data to obey Rayleigh distribution,at the same time,switch this radar echo data into point data,which applies to hardware emulation; And then when using hardware simulation, read the previous data file and deal it with constant false alarm rate processing.At last,the system will show hardware simulation results and waveform.

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Abstract:The traditional OFDM system as an important part of current wireless communication technology, its advantages are obvious, but one of shortcoming is easily affected by the frequency deviation. An effective solution is to improve data signal processing technology in the front of the system, thus can reduce the effects of system faults and improve the performance of the system. All phase data processing under the research idea of it is in this, after 20 years of research and development, now all phase FFT technology has been applied to image processing, signal processing, signal spectrum analysis, wireless communication transmission, etc. In this paper, using all phase FFT processing technology and detailed the APOFDM, Finally, using MATLAB simulation tools to analyze its advantages.

With the development of social productivity and the improvement of people's living standard, the development of modern computer technology is more and more fast. In the communication system, the code error detector is the important equipment to detect reliability of communication system, and the traditional code error detector is based on collaborative work of CPLD and CPU[1], not only is the structure complex, expensive, but it is inconvenient to carry. Code error detector based on FPGA, using FPGA to complete the integration of design of control and test module, to improve the scalability and integration of the system. This paper is based on principle of M sequence generation and code error detection, using the VHDL hardware description language, to realize the design of a simple bit by bit comparison code error detector and the simulation of each function module.

Network communication is very important in network transmission.With the continuous improvement of Ethernet technique,the transmission delay of Ethernet MAC(Medium Access Control)will influence communication quality of network.This paper realizes correct send-receive of the Ethernet MAC protocol layer data packet by FPGA,which can reduce transmission delay and enhance throughput rate so that avoid network congestion.It provides technical support of the development of gigabit Ethernet.