Design of Control unit for Low Power AU Using Reversible Logic

An important requirement of a digital system design is to reduce the power dissipation. Reversible logic is an emerging technique, which has the ability to reduce power dissipation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. There is no loss of bits during its computation, which results in reduction in power dissipation.In this paper, an 8-bit arithmetic and logic unit (ALU) using reversible logic circuits is proposed and designed in Verilog HDL.The synthesis and implementation result show that the proposed ALU improves by 39% in terms of power dissipation and 10% in terms of propagation delay over the ALU using conventional circuits. It has application in diverse fields such as low-power complementary metal oxide semiconductor (CMOS) design, optical information processing, cryptography, quantum computation and nanotechnology.

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“…The ALU has a 4-bit select input to select one from 16 operations as given in Table 1 [12]. Two 8-bit data are given …”

Section: Arithmetic and Logic Unitmentioning

confidence: 99%

Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit

Arunachalam¹,

Perumalsamy²,

Sundaram³

et al. 2014

International Journal of Computers and Applications

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“…Every reversible gate has a cost associated with it, called as Quantum cost. The simplest reversible gate is NOT gate and is a 1×1 gate [15]. The Reversible gate 2×2 with quantum cost of the reversible gate having mapping input (A,B) to output (P = A, Q = AB) is shown in Figure 2 that the combinational circuit diagrams of the NOT gate and CNOT gate [16].…”

Section: Basic Reversible Logic Gatementioning

confidence: 99%

“…Any reversible gate is optimized by using 1×1 NOT gates (inverter) and 2×2 (Feynman gate) Reversible gates, such as V, V + (V is the square root of NOT gate and V + is its Hermitian) and FG gate that is also known as CNOT gate. The properties of V and V + Quantum Gates are given in the following equation [17].…”

Section: Fig 2 Combinational Circuit Diagram Of 1x1 Not Gate and Cnomentioning

confidence: 99%

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Sharma¹,

Singh²,

Akashe³

2013

IJCA

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Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

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“…This concludes that general gates like "AND" and "OR" cannot be implemented through reversibility as multiple inputs bring down to a single output which was not in accordance to a reversibility concept as there is loss of information. The circuits with extremely less power consumption and doesn't need any sort of regular interconnections are an advantage [7]. This paper focuses upon the various architectures of reversible gates designed in QCADesigner tool with their graphical output waveforms while logic verification through the traditional truth table based methods.…”

Section: Introductionmentioning

confidence: 99%

Design and Verification of Reversible Logic Gates using Quantum Dot Cellular Automata

Shabeena¹,

Pathak²

2015

IJCA

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This paper portrays the designing of Reversible Logic gates through the use of Quantum Dot Cellular Automata (QCA) which is a nanotechnology concept and also a striking substitute for transistor based technologies. This technology helps us to rise above the confines of CMOS technology. It also gives better results in terms of digital and analog waveform, Quantum cost, garbage output. The fundamental logic in QCA is the logic state that does not compute with voltage level; rather it measures the polarity of electrons in a quantum cell. Basically Reversible logic gates are an essential building block of various computing system. Comparing with standard gates, the reversible logic gate lower the information bits use loss by reusing the logic information bits logically and realizes the goal of lowering power consumption of logic circuits. A QCAdesigner tool is used for simulation of different kinds of Reversible logic gates such as Toffoli gate, Fredkin gate and some others.

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Design of Control unit for Low Power AU Using Reversible Logic

Cited by 13 publications

References 18 publications

Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit

Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Design and Verification of Reversible Logic Gates using Quantum Dot Cellular Automata

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