Design of Efficient Content Addressable Memories in High-Performance FinFET Technology

Abstract

Content addressable memories (CAMs) enable highspeed parallel search operations in table lookup-based applications, such as Internet routers and processor caches. Traditional CAM design has always suffered from the high dynamic power consumption associated with its large and active parallel hardware. However, deeply scaled technology nodes, with multigate devices replacing planar MOSFETs, are expected to bring new tradeoffs to CAM design. FinFET, a vertical-channel gate-wraparound double-gate device, has emerged as the best alternative to planar MOSFET. In this brief, for the first time, we explore the design space of symmetric and asymmetric gate-workfunction FinFET CAMs. We propose several design alternatives and evaluate them in terms of their dc and transient metrics for different mismatch probabilities using technology computeraided design simulations with 22-nm FinFET devices. We also propose two orthogonal layout styles for CAM design and show that one of them (vertical-search line) outperforms the other (vertical-match line) in terms of total power (22.3%) and search delay (5.8%). Index Terms-Content addressable memories (CAMs),FinFET, parasitic extraction, technology computer-aided design (TCAD).

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

“…This script generates the 3D TCAD structures (boundary and mesh), which undergo device simulation to yield the final capacitance matrix. This matrix can then be plugged into a mixed-mode device simulation setup to capture the transient behavior of the circuit [2], [9]. We extend 32nm ALDS to the 22nm planar silicon-oninsulator (SOI) CMOS process (Fig.…”

“…While the impact of parasitic capacitances on transient behavior and dynamic stability of deeply-scaled memory circuits is well-studied using ALDS [2], [9], their analog and RF counterparts have remained relatively unexplored. In this paper, using ALDS, we investigate the parasitic capacitances in a 10 GHz voltage-controlled oscillator (VCO) circuit in a 22nm planar CMOS process, and study the significance of these capacitances in determining the frequency of oscillation.…”

AVAC: A Machine Learning based Adaptive RRAM Variability-Aware Controller for Edge Devices

“…Scaling down CMOS technology has led to increase in leakage power, primary concern in low-power circuits. The leakage current (for 1V programming voltage) can go as high as 15nA per bit cell (and even higher in some cases) in the current deepsubmicron nodes [18]. This leads to a leakage gain of 480nW per word-line of 32 bits (switching them off dynamically when not needed) in the proposed approach.…”

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories

“…Recent developments in 3-D CAM architecture, including 3-D partitioned MLs and SLs, result in reduced wordline capacitance and overall power consumption in ternary CAMs [57], [58]. In addition, recent advances in 3-D multigate transistor technology (FinFET) have been applied to CAM architectures, aiming to reduce the leakage power inherent to deep submicrometer processes, while reducing the dynamic power primarily contributed by the parallel search hardware in CAMs [59]. Just as new memory devices and circuit/architecture level design are being explored for use in CAM, many new applications are emerging today, more than 50 years after its invention.…”