Multi-gate CMOS devices promise to usher an era of transistors with good electrostatic integrity at the sub-22nm nodes, which makes it essential to rethink traditional approaches to designing lowleakage digital logic and sequential elements formerly used in highperformance planar single-gate technologies. In the current work, we explore the design space of symmetric (Symm-Φ G ) and asymmetric gate workfunction (Asymm-Φ G ) FinFET logic gates, latches, and flip-flops for optimal trade-offs in leakage vs. delay and temperature in a highperformance FinFET technology. We demonstrate, using mixed-mode Sentaurus technology computer-aided design (TCAD) device simulations, that Asymm-Φ G shorted-gate n/p-FinFETs, which use both workfunctions corresponding to typical high-performance n/p-FinFETs, yield over two orders of magnitude lower leakage without excessive degradation in onstate current, in comparison to Symm-Φ G shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independentgate (IG) FinFETs for leakage reduction. Results for elementary logic gates like INV, NAND2, NOR2, XOR2, and XNOR2 using Asymm-Φ G SG-mode FinFETs indicate that they are more optimally located in the leakage-delay spectrum in comparison to the most versatile configurations possible by mixing corresponding Symm-Φ G SG-and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-Φ G and Asymm-Φ G FinFETs to optimize leakage, delay, and setup time simultaneously.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.