Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

In this paper, we have calculated and described the Shift Register Design using FinFET. Shift Register is used as to shift the value of any register, in microprocessor, microcontroller and shifted value is also equal to multiplication of any binary no. by 2. According to Moore's law the no. of transistor in a scrupulous chip area is doubled in every 18 months. This proclamation gives new epoch of VLSI meadow. If we want to increase the no. of component in chip area so we reduce the size of component. Applying this attribute in chip component, the size of transistor reduced. As we scale down the device parameter after a certain rule, the short channel effects like leakage power, surface scattering, velocity saturations, takes place. Fin-FET is a superior device to eradicate or decrease above mentioned problems. We analyze the various parameters like temperature effect to the total power, total power consumption, average DC power, calculation etc. For calculation these results we are using cadence tools. After simulating the circuit we get values of Average DC power is 777.6 nW, Average Transient Power Consumption is 67.20 nW, Delay is 20 nS.

show abstract

“…Shift Register also acts as a counter. Shift Register is cluster of Flip-Flops [1][2][3]. Shift Register is intended via D Flip-Flop.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Shift Register in Nano Scale Domain Using FinFET

Gupta

Akashe

2015

Springer Proceedings in Physics

View full text Add to dashboard Cite

show abstract

“…The most effective way to reduce power and conserve area involves utilizing both shorted-gate and independent gate FinFETs [6]. The work function of each gate can even be modified which can not only improve power but can also, reduce the total [1] number of transistors by merging series and parallel combinations [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

“…Agostinelli et al compared the leakage and delay between FinFETs and bulk CMOS for several logic circuits; it was shown that FinFETs had considerably less leakage at the cost of an increase in delay [6]. Bhoj et al investigated the performance of asymmetrical work functions in shorted-gates, showing that asymmetrical shorted-gate devices could offer leakage control similar to independent gates without using additional area [7]. Meinhardt and Reis demonstrated that the use of independent gates can offer reduced leakage and an average 20% area reduction compared to shorted gate and planar CMOS in basic cells at the cost of additional delay [9].…”

Section: Introductionmentioning

confidence: 99%

Leakage and delay analysis in FinFET array multiplier circuits

Whitehouse

John

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

This paper investigates the performance of array multipliers utilizing FinFET models for the following feature sizes: 20nm, 16nm, 14nm, 10nm and 7nm. Using basic array multiplier topology and standard cell 28 transistor full adders, the static power and delay of FinFET array multiplier circuits were investigated using HSPICE and low power Predictive Technology Models (PTM). Simulation results show an increase in static power and a decrease in delay as the feature size decreases. Comparisons between array multiplier sizes show nonlinear increases in both static power and delay as size increases from 4x4 up to 16x16. The results obtained in this research will provide a starting point for the design and analysis of more complex FinFET based arithmetic circuit designs.

show abstract

“…These reductions have affected the static power dissipation of the circuits. This situation appears significantly in sub-22nm bulk CMOS technology because of very poor channel electrostatic potential which leads to degraded shortchannel behavior and high leakage current [1], [2]. FinFET transistors overcome these problems with a stronger control of the channel potential by using two gates wrapped around the fin [2].…”

Section: Introductionmentioning

confidence: 99%

Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs

Moshgelani

Al-Khalili

Rozon

2012

10th IEEE International NEWCAS Conference

View full text Add to dashboard Cite

In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through use of asymmetric work functions for the four terminal FinFET devices. We are also examining various transistor configurations and circuit topologies for logic gates using both symmetric and asymmetric work function transistors. Based on extensive characterization data, the logic gates using symmetric devices with one additional supply voltage have the best tradeoff between leakage current and performance. However, with asymmetric devices the leakage current drops by an average of 95% with degradation in delay of 8%. For a carry generation complex gate, our configuration, using symmetric devices, both leakage current and delay are improved by 35% and 47% respectively compared to results in the literature. Using asymmetric devices without additional supply achieves average improvements in leakage and delay of 81% and 5% respectively. All simulations are based on 25nm FinFET technology using the University of Florida UFDG model.

show abstract

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

Cited by 65 publications

References 15 publications

Design of Low Power Shift Register in Nano Scale Domain Using FinFET

Design of Low Power Shift Register in Nano Scale Domain Using FinFET

Leakage and delay analysis in FinFET array multiplier circuits

Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs

Contact Info

Product

Resources

About