Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

Bhoj, Ajay N.; Jha, Niraj K.

doi:10.1109/tvlsi.2013.2252031

Cited by 29 publications

(33 citation statements)

References 18 publications

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“…3. The read operation is obtained through ultra fast differential current compensation sense amplifier (DCC-SA) [38][39][40]. The read operation is performed by keeping read word line (RWL) to HIGH and write word line (WWL) to LOW and XNOR_I/P kept at LOW value.…”

Section: Operations and Working Of 10t Sram Using Differntial Currentmentioning

confidence: 99%

“…However, write'0' energy is improved by 1%, 6.2% and 5.2% as compared to RD8T, LP10T and LP9T SRAM, respectively at 300mV supply voltage. Furthermore, the read delay is measured when RWL is activated and precharged bit-lines discharges and reaches to the minimum sensing voltage required by SA [38][39][40]. In our proposed DCC-SA architecture [45][46][47], by estimating the read sensing voltage at worst case process corner, we examined a differential voltage of range 50mV-80mV required for generating an output signal to read data from SRAM.…”

Section: B Write and Read Analysismentioning

confidence: 99%

“…Due to superior gate control, improved electrostatic integrity and variability, FinFET have demonstrated satisfactory scalability and feasibility for mass production of post 22nm node. Thus, FinFET is an ideal alternative to planar CMOS in SRAM designs [37], [38]. However, while considering bulk-CMOS SRAM, the need of diminution in leakage power at subthreshold region has still a primary challenge.…”

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confidence: 99%

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Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh¹,

Vishvakarma²

2017

Preprint

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An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. IntroductionThe massive constrain headed for internet of things (IoT) devices has led to developments of ultra-low power (ULP) systemson-chip (SoCs) that are capable of operating in sub-threshold voltages [1,2]. One way to guarantee low power and energy consumption is to scale down the supply voltage to the sub-threshold region [3]. However, the reduced on-to-off current ratio (I ON /I OFF ) and the exponential dependence of the current on the threshold voltage (V th ) in the sub-threshold region introduces many challenges especially in rationed circuits such as the traditional 6T static random access memory (SRAM) bit-cell. Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicabi...

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Section: Operations and Working Of 10t Sram Using Differntial Currentmentioning

confidence: 99%

Section: B Write and Read Analysismentioning

confidence: 99%

mentioning

confidence: 99%

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Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Singh¹,

Vishvakarma²

2017

Preprint

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“…Accurate estimation of parasitic capacitances is becoming a key step in state-of-the-art post-layout industrial VLSI design flows as it determines the timing, power, and dynamic stability of the integrated circuits (ICs) [1], [2]. These estimated capacitances provide feedback to the designers regarding the final functionality and performance of the design, before silicon integration.…”

Section: Introductionmentioning

confidence: 99%

“…While the impact of parasitic capacitances on transient behavior and dynamic stability of deeply-scaled memory circuits is well-studied using ALDS [2], [9], their analog and RF counterparts have remained relatively unexplored. In this paper, using ALDS, we investigate the parasitic capacitances in a 10 GHz voltage-controlled oscillator (VCO) circuit in a 22nm planar CMOS process, and study the significance of these capacitances in determining the frequency of oscillation.…”

Section: Introductionmentioning

confidence: 99%

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

Bhattacharya

Joshi

Ainspan

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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With continued scaling of bulk CMOS devices in the nanometer regime, technology computer-aided design (TCAD) assisted extraction of parasitic capacitances has gained importance for predicting the transient behavior of VLSI circuits. In this paper, we present a TCAD structure synthesis and capacitance extraction methodology in a 22nm CMOS process and report parasitic capacitances that affect the oscillation frequency of a 10 GHz voltage-controlled oscillator (VCO). We observe that front-end capacitances are becoming overwhelmingly dominant at nanometer nodes. We quantify the capacitive interactions between the front-end and back-end features using a layer-bylayer capacitance analysis. The estimated frequency tuning range is in agreement with the tuning range of a 22nm VCO hardware.

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Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes

Agarwal

Chandel

2021

Lecture Notes in Electrical Engineering

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Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

Cited by 29 publications

References 18 publications

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology

Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes

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