Ultra Low Power Process Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications

Abstract

An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.Keywords: power gating; read decoupling; read-write static noise margin; dynamic noise margin; read-write energy; schmitt trigger; leakage power. IntroductionThe massive constrain headed for internet of things (IoT) devices has led to developments of ultra-low power (ULP) systemson-chip (SoCs) that are capable of operating in sub-threshold voltages [1,2]. One way to guarantee low power and energy consumption is to scale down the supply voltage to the sub-threshold region [3]. However, the reduced on-to-off current ratio (I ON /I OFF ) and the exponential dependence of the current on the threshold voltage (V th ) in the sub-threshold region introduces many challenges especially in rationed circuits such as the traditional 6T static random access memory (SRAM) bit-cell. Since, conventional non-volatile memories consume higher read and write power, the scaling of supply voltages and the techniques to reduce leakage at sub-threshold voltages needed. However, the low cell stability is also one of the factor which defy conventional SRAM architecture to not to work at sub-threshold region [4].However, due to rapid growth of internet market through all over the world, Internet of Things (IoT) brings connectivity, communication, and data gathering to existing devices. IoT includes countless devices connected and communicated with each other to enrich the present lifestyle, and its applicabi...

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

“…2) RDNM: The Read dynamic Noise Margin (RDNM) is defined by the voltage difference of storage node Q and QB when read bit line reach to sensing voltage during read operation [26]. The RDNM of the proposed SRAM is 29.23% and 13.91% better than C6T and Transpose 8T [15] SRAM, respectively, as observed from Table I…”

Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability

“…All these memories are charge-based. In SRAM, the data are stored as charges at the nodes of the cross-coupled inverters [2,3]. SRAM has been widely used in the memory market.…”

Non-volatile SRAM memory cells based on ReRAM technology

“…Clock gating technique is used for reducing dynamic power by controlling switching activities on the clock path [9]. In the case of power gating, certain areas of the chip are idle and other parts are activated only for certain operations [10]. In this context, emerging Non-Volatile Memory (NVM) devices can act as key enablers in the development of ultra-low power (ULP) MCUs [11].…”