Fault Models for Logic Circuits in the Multigate Era

Bhoj, Ajay N.; Simsir, Muzaffer O.; Jha, Niraj K.

doi:10.1109/tnano.2011.2169807

Cited by 28 publications

(14 citation statements)

References 18 publications

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“…Currently, few researches have been carried out on fault modeling of the FinFET, and Carbon NanoTubes (CNTs). The authors in [12,13] investigated open and short faults on FinFETs, and they showed that Stuck-at Open Faults (SOFs) on the back gate of FinFET have a unique effect on the leakage and delay. In [16], the GOS defect on the Fin-FET dielectric have been studied .…”

Section: Background and Motivationmentioning

confidence: 99%

“…For instance, stuck-at [8], delay [9], stuck-open [10], and bridging fault [11] are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts [12,13], stuck-open/stuck-on [14,15], and Gate Oxide Short (GOS) [16]. These studies revealed the deficiency of current CMOS fault models for detecting defects in FinFET circuits, and necessitated a new fault model for test generation purpose.…”

Section: Introductionmentioning

confidence: 99%

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Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.

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Section: Background and Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Mohammadi¹,

Gaillardon²,

Micheli³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

View full text Add to dashboard Cite

show abstract

“…Currently, few researches have been carried out on fault modeling of the FinFET. Simsir et al,in [15] and [16] investigated open and short faults on FinFETs, and they showed that stuck-Open faults (SOFs) on the back gate of FinFET have a unique effect on the leakage and delay. In [19], the GOS defect on the FinFET dielectric has been studied.…”

Section: Background and Motivationmentioning

confidence: 99%

“…For instance, stuck-at [11], delay [12], stuck-Open [13], and bridging fault [14] are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts [15], [16], stuck-Open/stuckOn [17], [18], and gate oxide short (GOS) [19]. These studies revealed the deficiency of current CMOS fault models for detecting all the defects in FinFET circuits, and required the introduction of new fault models for test generation purpose.…”

Section: Introductionmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

Gaillardon

Micheli

2015

IEEE Trans. Nanotechnology

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Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

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“…While it is dedicated to the scaling down of the CMOS technology, the development of a gate-level model for FinFET is required. Let us cite work from Niraj Jha's group fault models for logic circuits in FinFET technology [13].…”

Section: Introductionmentioning

confidence: 99%

Gate-level modeling for CMOS circuit simulation with ultimate FinFETs

Chevillon

Madec

Lallement

2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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With the high complexity of current digital circuits, the use of gate-level models during the design process is mandatory. For standard CMOS technologies, designers assemble standard cells for which the gate-level model is provided by the founderies. For a given technology, the temporal parameters (such as propagation delays) are constants that can be extracted from experimental measurements. For FinFET-based circuits, such standard cells do not exist. As a consequence, to get predictive simulations of a circuit, the use of low-level model is required. To overcome this problem, we develop a predictive gate-level model for such circuits. To feed the timing parameters of the models, an automated procedure is established. It is based on a new compact model for ultimate FinFET mostly based on physical equations we recently develop. The results obtained with both approaches (compact model and gate-level model) are compared in the last part of the paper. For a digital circuit with about 80 transistors, the results are in accordance. The slight inaccuracy of the gate-level model is largely compensated by a very short simulation time.

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Fault Models for Logic Circuits in the Multigate Era

Cited by 28 publications

References 18 publications

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Gate-level modeling for CMOS circuit simulation with ultimate FinFETs

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