Design of Efficient Reversible Binary Comparator

Rangaraju, H G; Hegde, Vinayak; Raja, K.; Muralidhara, K. N.

doi:10.1016/j.proeng.2012.01.943

Cited by 17 publications

(15 citation statements)

References 6 publications

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“…This block comprises of an NFT block and two MIG gates and one TVG gate. The basic design of this block is based on [7]. The design is shown in Fig.…”

Section: Proposed 1-bit Comparator Blockmentioning

confidence: 99%

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Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Jayashree

Agarwal

Charan

et al. 2014

International Conference on Circuits, Communication, Control and Computing

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Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.

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“…This block comprises of an NFT block and two MIG gates and one TVG gate. The basic design of this block is based on [7]. The design is shown in Fig.…”

Section: Proposed 1-bit Comparator Blockmentioning

confidence: 99%

“…This paper presents the design of n-bit reversible fault tolerant comparator. There are a few reversible comparators [6,7,8,9,10,11] but with number of garbage outputs being on the higher side. The proposed design outperforms the previous designs [8,10] in terms of garbage outputs and constant inputs.…”

Section: Introductionmentioning

confidence: 99%

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Jayashree

Agarwal

Charan

et al. 2014

International Conference on Circuits, Communication, Control and Computing

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show abstract

“…The Controlled-V and Controlled-V + Gates The Quantum cost of a Reversible gate is computed by counting the number of V, V + and CNOT gates [11]. The controlled-V and V + gates are shown in Figures 1(b) and (c).…”

Section: Basic Reversible Gatesmentioning

confidence: 99%

Design of Low Power Comparator Using DG Gate

Dehghan¹,

Roozbeh²,

Zare³

2014

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In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V + gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

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“…In recent years reversible logic has received great attention to reduce the power dissipation. A Novel low power comparator design using reversible logic has been presented in [6]- [8] which have ability to reduce the power dissipation. The proposed design full fills the requirement of less power consumption in various applications like ultra low power digital circuit and quantum computers.…”

Section: Fig 4: 2-bit Comparator Using Transmission Gate Logic [5]mentioning

confidence: 99%

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

Sharma¹,

Singh²,

Kajla³

2013

IJCA

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In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 NMOS and 8 PMOS. A PTL and GDI full adder module has been used which consume less area at 120 nm as compared with the previous full adder designs. The proposed Hybrid 1-bit comparator design is based on this area efficient 9T full adder module. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the used full adder module. Full adder modules outputs have been used for the generation of three different output of 1-bit comparator designs. The proposed 1-bit comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed 1-bit comparator design. Power and current variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 329.3µm 2 on 120nm technology. At 1.4V input supply voltage the proposed 1-bit hybrid comparator consume 0.367mW power at BSIM-4 and 0.411mW power at LEVEL-3 and 2.313mA current at BSIM-4 and 3.047mA current at LEVEL-3 model

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Design of Efficient Reversible Binary Comparator

Cited by 17 publications

References 6 publications

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Design of Low Power Comparator Using DG Gate

Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic

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