Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit

Abstract

This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit.

Low power architecture of logic gates using adiabatic techniques

“…Further, energy efficient different gates are design using various adiabatic approach like CMOS, 2N2P, efficient charge recovery logic (ECRL) and PFAL adiabatic logic for low power applications [8]. A energy efficient AND/NAND and XOR/XNOR gates and carry lookahead adder are designed using noval charge sharing improved pass gate adiabatic logic (CSIPGL) technique which is operating uses four-phase power clock sources [9]. In recent years, much investigation has been reported on the design of inverter [10], gates [11]- [16], adder [17]- [22], subtractor [23], multiplexers [24], [25] and flip flops [26]- [28].…”