Design of fixed-point high-performance FFT processor

Li, Wenqi; Wang, Xuan; Sun, Xiangran

doi:10.1109/icetc.2010.5529796

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…x [1] x [2] x [3] x [4] x [5] x [6] x [7] x [8] x [9] x Butterfly architecture can either be serial-parallel, where data is operated on one bit at a time, or it can be processed in parallel as bit vectors. Serial-parallel butterfly architecture lends itself well for partitioning very large FFTs across several FPGA parts, since each data path is only one signal/pin.…”

Section: Software Defined Fft Parametersmentioning

confidence: 99%

CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation

Schmuland

Jamali

Longbrake

et al. 2012

10th IEEE International NEWCAS Conference

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Hand-coding Fast Fourier Transforms (FFTs) inHardware Description Language (HDL) is time consuming and prone to errors. Proprietary IP cores are available, however they are closed-source and unviewable. The open-source FFT generator SPIRAL is available, however it only produces parallel arithmetic solutions and thus limits the maximum FFT size that will fit in available Field Programmable Gate Arrays (FPGAs). An autogenerator of VHDL FFTs is described that takes a set of FFT parameters and generates an FFT component with feedback of occupied slices, maximum frequency, and dynamic range performance. Both parallel arithmetic and serial-parallel butterfly architectures can be generated where serial-parallel allows larger sized FFTs to fit inside available FPGA parts. Emphasis is placed on large sized serial-parallel FFTs and portability to Application-Specific Integrated Circuits (ASICs) using Cadence Encounter. Serial-parallel FFT pipeline control and FPGA hardware reduction are also investigated.

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Section: Software Defined Fft Parametersmentioning

confidence: 99%

CAD tool autogeneration of VHDL FFT for FPGA/ASIC implementation

Schmuland

Jamali

Longbrake

et al. 2012

10th IEEE International NEWCAS Conference

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“…All these approaches and others such as and , assume that the input is uniformly distributed to simplify the analysis. On the contrary, multipath signals are received at the OFDM receiver and hence, the input distribution is usually considered as Gaussian distributed.…”

Section: Fixed Point Optimizationmentioning

confidence: 99%

“…Second, the traditional twiddle multiplier uses four real multipliers, one addition, and one subtraction. To reduce the complexity, the multiplier architecture presented in has been utilized where only three multipliers, three adders, and two subtraction units are involved. The remaining building blocks will be discussed in details.…”

Section: Fast Fourier Transform Processor Implementationmentioning

confidence: 99%

A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

Ali

Hamouda

2015

Wireless Communications

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In this paper, we present 64/128/256/512-point inverse fast Fourier transform (IFFT)/FFT processor for single-user and multi-user multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11ac wireless local area network transceiver. The multi-mode processor is developed by an eight-parallel mixed-radix architecture to efficiently produce full reconfigurability for all multi-user combinations. The proposed design not only supports the operation of IFFT/FFT for 1-8 different data streams operated by different users in case of downlink transmission, but also, it provides different throughput rates to meet IEEE 802.11ac requirements at the minimum possible clock frequency. Moreover, less power is needed in our design compared with traditional software approach. The design is carefully optimized to operate by the minimum wordlengths that fulfill the performance and complexity specifications. The processor is designed and implemented on Xilinx Vertix-5 field programmable gate array technology. Although the maximum clock frequency is 377.84 MHz, the processor is clocked by the operating sampling rate to further reduce the power consumption. At the operation clock rate of 160 MHz, our proposed processor can calculate 512-point FFT with up to eight independent data sequences within 3.2~s meeting IEEE 802.11ac standard requirements.

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