Design of High Speed and Power Efficient Ternary Prefix Adders using CNFETs

Vudadha, Chetan; Srinivas, M.B.

doi:10.1109/tnano.2018.2832649

Cited by 22 publications

(16 citation statements)

References 24 publications

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“…The ternary equivalent for the binary logic 0 and 1 is logic 0 and 2 respectively. The existing ternary prefix adder [19] involves six stages of computations. In the initial stage, the ternary decoders are used to transform the ternary inputs into the binary values.…”

Section: Existing Ternary Prefix Addermentioning

confidence: 99%

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Shanmugam¹,

Kumar²

2022

Preprint

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Ternary adders have produced more benefits compared to the binary adders (i.e.) the ternary adder occupies less amount of area as well as produces less interconnect complexity. But the CMOS implementation of the ternary adders are failed to perform the process when the channel length is taken as 32nm. At 32nm technology, the CMOS transistors are exhibited undesired effects such as SCE, mobility degradation, etc., These issues are overcome by multi-gate devices. CNFETs (Carbon Nano-tube Field Effect Transistors) are the one of the technology to work efficiently when channel length is 32nm. In this paper, CNFETs based ternary prefix adders are designed. The power consumption is the most needed requirement for the VLSI system. So, this can be achieved by reducing the number of transistors. The reduction approach is called as the GDI (Gate Diffusion Input) logic is also included in the proposed prefix adder design. The proposed adder improved by reducing the power upto 83%, Energy upto 83%, current upto 78%, delay upto 96%. Finally, the PDP (Power Delay product) also reduced by 84% compared to existing ternary adders.

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Section: Existing Ternary Prefix Addermentioning

confidence: 99%

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Shanmugam¹,

Kumar²

2022

Preprint

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“…1) The proposed designs do not use standard logic gates, ternary decoders, or ternary encoders, which produce high transistors count and PDP ( [12]- [15], [25], [26]). 2) The proposed designs work on unary operators, which reduces the number of transistors ( [17]- [22], [28], [29]).…”

Section: Contributionsmentioning

confidence: 99%

Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

et al. 2021

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The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies (V dd and V dd /2). The result of extensive HSPICE simulations regarding PVT (Process, Voltage, and Temperatures) variations and Noise Immunity Curve (NIC) show the improvements of the proposed designs up to 25% in transistors count and up to 98% in energy consumption reductions. Further, increasing the robustness of process variations and the noise tolerance compared to recent similar designs.

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“…In [30], the authors proposed THA with 90 CNTFETs and TMUL with 62 CNTEFTs using RRAM. The authors of [31] proposed two THAs with 94 and 66 CNTFETs and the authors of [32] proposed THA with 64 CNTFETs using TDecoders and special transistors arrangements. Whereas in [33], the authors proposed a THA with 60 CNTFETs using ternary encoders and special transistors arrangments.…”

Section: A Literature Reviewmentioning

confidence: 99%

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

2021

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Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

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Design of High Speed and Power Efficient Ternary Prefix Adders using CNFETs

Cited by 22 publications

References 24 publications

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

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