Design of high speed approximate multipliers with inexact compressor adder

Abstract

In most practical applications, accurate results are unnecessary, hence approximate computation is being used. By using approximate computing the system performance metrics like area, power and speed can be improved. This paper proposes an approximate circuit that was developed by modifying the circuit architecture but not the circuit operation. We propose an approximate multiplier using these approximate circuits, which use AND-OR logic approximation, Wallace tree reduction, and 3:2 inexact additive designs for partial product generation and addition. In this paper, by taking an 8X8 bit multiplication as an example, we show the whole proposed concept. Also, the proposed multipliers will cause substantial improvements in terms of both area and delay. Compared to the conventional multipliers, the AWM1 achieves up to 35.577% reduction in area and 35.224% in delay. AWM2 has an area and delay reductions of up to 48.077% and 36.532% respectively. AWM3 has area savings of up to 48.077% and delay reductions of up to 46.633%. Finally, the AWM4 has area savings of up to 53.846% and delay reductions of up to 56.482%.

Error efficient LOB-based approximate multipliers for error-tolerant applications

“…However, accuracy remains a concern for high-input widths. Next, area and powerefficient AMs utilize low-power devices in compressors to enhance performance but have accuracy contingent on compressor size [30].…”