Design of High-Speed Floating Point Multiplier

IEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers

“…The bottleneck of floating point multiplication is mantissa multiplication which needs 53*53 bit integer multiplier for double precision floating point numbers. There are many multiplier architectures using different multiplication techniques for example, Array multiplier, redundant binary architecture and many more architectures using tree structures but they have problem of larger delay [1][2][3][4][5]. Different algorithms are also there that perform floating point multiplication like BOOTH algorithm, algorithms based on ancient mathematics [11], and many more.…”

“…It involves three operations. Exponents of multiplier and multiplicand are added, mantissas of two numbers are multiplied and ex-or of sign bits is done to get final sign bit [1][2][3][4][5][6][7][8][9][10].…”

“…In BOOTH multiplication algorithm to reduce the time needed for multiplication number of partial products to be added are reduced [1][2][3]. BOOTH recording reduces the number of adder units needed and hence reduced the delay by reducing number of nonzero bits in the multiplier [2].…”

“…BOOTH recording reduces the number of adder units needed and hence reduced the delay by reducing number of nonzero bits in the multiplier [2]. In BOOTH recoding, the long sequence of 1s is replaced by two no zero bits; for example, If digits j through (down to) k are 1s, then,…”

“…FPGA based floating point multiplication can be categorized as IP core based and algorithm based [1][2]. In IP core based highly optimized IP cores are employed as sub units of floating point unit design and in algorithm based implementation techniques are employed to get better performance by grading system goals as speed, area and throughput optimizations [2][3][4][5].…”