Design of high‐speed, low‐power, and area‐efficient FIR filters

Abstract

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.

Radix‐2 r recoding with common subexpression elimination for multiple constant multiplication

“…Based on the Radix‐2 r arithmetic, we have developed in previous work [2–5] a new heuristic called Radix‐2 r MCM. It has the major advantage of being fully predictable in the maximum number of additions (upper‐bound), in the average number of additions, and in the number of cascaded adders (adder‐depth) forming the critical path.…”

“…Furthermore, it requires sub‐linear computational complexity O ( M × N / r ), where M is the number of constants, N is the bit‐length of the constants, and r is a function of ( M , N ). This means that Radix‐2 r MCM has no limited applicability regarding the complexity of the problem, contrary to most existing algorithms [4, 5].…”

“…We have demonstrated in [5] that Radix‐2 r MCM leads to a near‐optimal solution in adder‐depth without sacrificing the adder‐cost. Furthermore, we have analytically and experimentally proved [5] through the physical implementation of many benchmark FIR filters of different complexities the superiority of Radix‐2 r MCM in handling medium/high order filters in comparison to the most area‐efficient algorithms, notably to the cumulative benefit heuristic (Hcub) [6] known for its lowest adder‐cost.…”

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder

“…The FIR filter coefficients change rapidly during execution time, in several application scenarios such as a digital up-converter, digital down converter, multi-channel filter and software-defined radio systems [3,4]. Compared to the conventional non-RFIR filter designs with reconfiguration / without reconfiguration, RFIR filters were consuming less resource and power [5]. The discrete FIR filtering detects extensive utility in low-power and highperformance Embedded Computing Systems (ECS) that range from wireless transmitters/ receivers to image and video processing units [6].…”

Low Cost FPGA Implementation of RFIR Filter Based on a Radix-4 Algorithm

“…The RFIR filter coefficients change dynamically when runtime plays a vital PART in the Software Defined Radio (SDR), digital up or down converters and so on [4,5]. Compared to the existing non-RFIR filter designs with reconfigurable and without reconfigurable, that RFIR filters consumeless power [6]. In recent years, the different implementation techniques and system architectures have been proposed to increase the performance of the RFIR filter in terms of reducing system complexity and high-system performance [7].…”