Design of Instruction List Processor for Industrial Applications

Shedge, Sagar; Tade, Sunil L.

doi:10.1109/iccubea.2018.8697869

Cited by 4 publications

(3 citation statements)

References 2 publications

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“…Both processors were developed as specialized structures capable of the execution of control routines developed in the Instruction List programming language, in line with the requirements of the EN 61131-3 standard. Another paper [10] proposed an Instruction List (IL) processor compatible with the IEC 61131-3 standards. A three-stage pipeline was applied so that each instruction was executed in a single machine cycle, providing high execution speed.…”

Section: Introductionmentioning

confidence: 99%

“…A five-stage pipeline was proposed to increase the operation speed. Another IEC 61131-3 Instruction List processor was briefly described in [12]. In [13], an architecture based on an existing RISC-V processor targeted for the implementation of a PLC on FPGA was presented.…”

Section: Introductionmentioning

confidence: 99%

“…Only a few of the aforementioned papers, namely [9][10][11][12], directly considered the IEC 61131-3 IL instruction list as an instruction set for designed CPUs. Some of them (i.e., [11,12]) revealed very few details about the proposed architecture or its features. Additionally, in most cases, only a limited subset of IL instructions was implemented.…”

Section: Introductionmentioning

confidence: 99%

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IEC61131-3 Instruction List Language Processor for FPGAs

Hajduk

2023

Electronics

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This paper presents the architecture and field-programmable gate array (FPGA) implementation of a 32-bit central processing unit (CPU) dedicated to programmable logic controllers (PLCs). The CPU instruction set directly matches the instructions of the IEC 61131-3 standard Instruction List (IL) language. The designed IL processor is capable of handling 1-bit, 8-bit, 16-bit, and 32-bit data types. Apart from integer arithmetic operations, the IL processor also performs single precision floating-point operations included in the IEC 61131-3 IL language specification. It also directly performs instructions with a parenthesis modifier for all supported data types and facilitates the fast execution of a code containing Boolean expressions. This paper also presents the performance evaluation results of the developed IL processor. Although the IL processor executed the test algorithms substantially faster than industrial PLCs (e.g., Siemens S7-1200 and Fanux VersaMax), it turned out to be significantly slower than high-performance programmable automation controllers (PACs).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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IEC61131-3 Instruction List Language Processor for FPGAs

Hajduk

2023

Electronics

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Low-Latency FPGA-Based PLC Microprocessor for Industrial Automation in Compliance with IEC-61131-3

Cancino-Escobar,

Delgado-Del-Carpio,

Solís-Cisneros

et al. 2024

Arab J Sci Eng

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This study presents the design and implementation of a PLC microprocessor adhering to the IEC-61131-3 standard, executed on a Cyclone-V FPGA using a DE10-NANO development board. Our microprocessor optimizes the central processing unit by streamlining the data path, achieving a remarkable simulated response time of approximately 60 ns, equivalent to three clock cycles at a 50MHz frequency for Boolean operations. To substantiate our approach, we conducted practical experiments utilizing a FESTO conveyor station, employing relays as actuators, and incorporating optical and inductive sensors. The results underscore the feasibility of our proposed approach and serve as practical validation of its efficacy. This work introduces a promising avenue for the development of cost-effective PLCs employing SoC FPGA variants. Additionally, a thorough comparison of execution times with other early reported architectures. Our microprocessor outperforms even well-established PLCs like the S7-312, with substantial reductions in execution times of 94.54% for floating-point operations, 71.42% to 93.33% for word operations, and up to 78.57% for bit operations.

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Designing of 32-Bit Configurable Hack CPU On FPGA

Kawle

Thakare

2021

2021 6th International Conference on Communication and Electronics Systems (ICCES)

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Design of Instruction List Processor for Industrial Applications

Cited by 4 publications

References 2 publications

IEC61131-3 Instruction List Language Processor for FPGAs

IEC61131-3 Instruction List Language Processor for FPGAs

Low-Latency FPGA-Based PLC Microprocessor for Industrial Automation in Compliance with IEC-61131-3

Designing of 32-Bit Configurable Hack CPU On FPGA

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