IEC61131-3 Instruction List Language Processor for FPGAs

Abstract

This paper presents the architecture and field-programmable gate array (FPGA) implementation of a 32-bit central processing unit (CPU) dedicated to programmable logic controllers (PLCs). The CPU instruction set directly matches the instructions of the IEC 61131-3 standard Instruction List (IL) language. The designed IL processor is capable of handling 1-bit, 8-bit, 16-bit, and 32-bit data types. Apart from integer arithmetic operations, the IL processor also performs single precision floating-point operations included in the IEC 61131-3 IL language specification. It also directly performs instructions with a parenthesis modifier for all supported data types and facilitates the fast execution of a code containing Boolean expressions. This paper also presents the performance evaluation results of the developed IL processor. Although the IL processor executed the test algorithms substantially faster than industrial PLCs (e.g., Siemens S7-1200 and Fanux VersaMax), it turned out to be significantly slower than high-performance programmable automation controllers (PACs).

Verification of Control System Runtime Using an Executable Semantic Model

“…(cm, dm, cs, ds, cr, dr, ex, f lg) := s ig := Get1BMem(cr, cm) cr 1 := cr ⊕ 1 it := Get1BMem(cr (17) According to [25] or [26], λ-expression has the form of λs.body, where s denotes the current state, and body determines the value returned by the function. The computation of function U begins with fetching the instruction group byte (ig), which is located in the code memory (cm) at the address indicated by the current value of the code register (cr).…”

“…Two examples of instruction groups are given in Formula (17). The ig=01 denotes addition instructions, while ig=04 denotes the division ones.…”

“…A high degree of universality is achieved by implementing a large part of the virtual machine in C/C++ languages available for numerous hardware platforms and processors [14]. Another solution, emphasizing performance, is to implement it in the languages for FPGA circuits [15][16][17].…”