Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization

Abstract

In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from a placer, we formally define a class of netlist transformations that produce different netlists from the given netlist but have the same Half-Perimeter Wire Length (HPWL). Furthermore, the optimal HPWL value of the new netlists is no less than that of the original netlist. By applying our transformations and re-executing the placer, we can interpret any deviation in HPWL as a lower bound to the deviation from the optimal HPWL value. Such deviation is a measure of suboptimality. Using these transformations, the suboptimality of several existing academic and industrial placers is studied on the IBM benchmarks. Our results show that current placers are suboptimal for zero-change transformations with deviations in HPWL by up to 32% on the IBM (version 1) benchmarks. The specific nature of our transformations also pinpoints possible directions for improvement in existing placers.

Wire density driven global routing for CMP variation and timing

“…This implies that just congestion-driven global routing cannot address the wire density issue efficiently. Furthermore, we observe that wire delay is near linearly proportional to wire density in global routing even with CMP effect (dishing/erosion and dummy fill) [9,20,29] and scattering effect [15] taken into consideration.…”

“…Even after CMP, intra-chip topography variation can still be on the order of 20-40% [9,21]. Such topography variation leads to not only significant performance degradation due to increased wire resistance and capacitances, but also acute manufacturing issues like etching and printability [7,9,21,23].…”

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

“…1) CMP aware Routing: Topography (thickness) variation after CMP is shown to be systematically determined by wire density distribution [13]- [17]. Even after CMP, intra-chip topography variation can still be on the order of 20-40% [13], [18]. Such topography variation leads to not only significant performance degradation due to increased wire resistance and capacitances, but also acute manufacturing issues like etching and printability [13], [16]- [18].…”

“…Even after CMP, intra-chip topography variation can still be on the order of 20-40% [13], [18]. Such topography variation leads to not only significant performance degradation due to increased wire resistance and capacitances, but also acute manufacturing issues like etching and printability [13], [16]- [18]. The main reason for the copper CMP problems is wire density distribution.…”

Detailed Placement for Enhanced Control of Resist and Etch CDs

“…In addition, metal dishing and dielectric erosion change interconnect cross section and, therefore, affect interconnect resistance. He et al [18] report an increase of more than 30% in interconnect resistance due to dishing and erosion, while the impact on interconnect capacitance is insignificant. He et al [19] also propose a wire-sizing approach to lessen the amount of interconnect-resistance variation due to the CMP process.…”