Design of less time delay multiplier using vedic mathematics

Dogra, Megha; Balamurugan,

doi:10.1109/get.2016.7916696

Cited by 3 publications

(1 citation statement)

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“…Among 3 designs 1-D9/7 DWT occupies the least area and maximum combinational path delay [15]. In the same year, 2015 Akanksha Kant and Shobha Sharma have suggested what are the possible applications (like image processing and digital signal processing) of Vedic mathematics [16].…”

Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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The usual segmentation methods were addressed here: edge detection, clustering, and region growth. The problem with segmentation is that no one approach is suited for a certain type of picture, nor are all techniques applicable to all images. The importance of multiplication is rising according to the technology process. It is one of the major applications which is used in various domains such as business and digital signal process etc. The way of general multiplication is much more time taking process. So, mainly as to remove this time delay in this paper the concept of Vedic mathematics is introduced. This paper introduced about Indian ancient Vedic mathematics is involved to clear those problems. Sixteen sutras among the Vedic mathematics the one sutra that is widely used and implemented is “URDHVA-TIRYAGBHYAM” is proposed. The multiplication process of two 4 bit and two 3 bit and also two 2-bit multiplications are gone through this paper. This process ultimately leads to the consumption of less time and faster implementation. But, with respect to the order of multiplication, the complexity will also increase. When compared to other multipliers it takes less area.

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Section: Literature Reviewmentioning

confidence: 99%