Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Oliveira, Duarte L.; Bompean, Diego; Curtinhas, Tiago; Faria, Lester A.

doi:10.1109/lascas.2013.6519027

Cited by 8 publications

(5 citation statements)

References 17 publications

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“…As disadvantages, it presents a little reduction of the asynchronous logic requirements in the logic synthesis steps and BM specification shows to be limited to describe interactions with synchronous data-path, because it does not accept LSS signals. In order to eliminate the problem of logic minimization, which has to be free of logical hazard, and the limitation of the BM specification, which does not accept signals LSS, Oliveira et al [9] proposed a state assignment technique for XBM_AFSM with local clock in the Huffman architecture with output feedback. Then, Curtinhas et al [10] implemented the states assignment technique of [9] using genetic algorithm.…”

Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

“…In order to eliminate the problem of logic minimization, which has to be free of logical hazard, and the limitation of the BM specification, which does not accept signals LSS, Oliveira et al [9] proposed a state assignment technique for XBM_AFSM with local clock in the Huffman architecture with output feedback. Then, Curtinhas et al [10] implemented the states assignment technique of [9] using genetic algorithm. The paper of [9] proposed an architecture with local clock based on flip-flops, focusing on FPGA platforms.…”

Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

“…Then, Curtinhas et al [10] implemented the states assignment technique of [9] using genetic algorithm. The paper of [9] proposed an architecture with local clock based on flip-flops, focusing on FPGA platforms. This proposal presents, as advantages, when compared to the proposal of [3], the use of the output signals as state variables, what potentially generates smaller machines and accepts the XBM specification.…”

Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

“…It follows the conventional steps of logic synthesis and starts from the XBM specification. As in [9][10][11], the only restriction is not accepting the "directed don't-care" signals of the XBM specification. The steps of transforming the XBM specification in a Kiss2 description and generation and analysis of the dependency graph are performed by the proposed XBM_DG tool.…”

Section: Extended Burst Mode Specification (Xbm)mentioning

confidence: 99%

See 3 more Smart Citations

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools

Oliveira

Tuyama

Curtinhas

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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⎯ Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines Asynchronous (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This paper proposes a new architecture of local clock to AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture has a better cycle time when compared to other local clock architectures. Also, the paper proposes a "necessary and sufficient" condition for the local clock AFSMs on the proposed architecture to be synthesized completely by the use of conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and compare it with other local clock architectures, highlighting its advantages.

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Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

Section: A Locally Clocked Xbm/bm Afsms: Overviewmentioning

confidence: 99%

Section: Extended Burst Mode Specification (Xbm)mentioning

confidence: 99%

See 2 more Smart Citations

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools

Oliveira

Tuyama

Curtinhas

et al. 2016

2016 IEEE 7th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

View full text Add to dashboard Cite

show abstract

“…Genetic algorithms are sometimes applied in the process of coding [15], [16]. The search for more efficient implementations of automatons is sometimes carried out also in the form of a globally asynchronous locally synchronous (GALS) [17] structure, or solutions exploiting clock gating [18], [19].…”

Section: Introductionmentioning

confidence: 99%

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

2019

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A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function. The main contribution is the novel multilevel optimization of an FSM. In this process, a new form of graph is used, i.e., a graph of excitations and outputs. This is a generalization of the graph of outputs that has previously been used in the process of technology mapping of multi-output functions in PAL-based programmable structures. The main idea, the theoretical background, and a precise algorithm are illustrated by means of simple examples. The proposed algorithm was compared with other approaches by synthesizing the FSM benchmarks and mapping the solutions to k-term PAL-based logic blocks. The obtained results are compared on the basis of the area (number of logic blocks) and speed (number of logic levels). The proposed approach is especially effective for larger FSMs. INDEX TERMS CPLD, FSM, multi-level optimization, technology mapping.

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Combined State Splitting and Merging for Implementation of Fast Finite State Machines in FPGA

Klimowicz

2020

Lecture Notes in Computer Science

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Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Cited by 8 publications

References 17 publications

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

Combined State Splitting and Merging for Implementation of Fast Finite State Machines in FPGA

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