Design of Low-Cost Approximate CMOS Full Adders

Abstract

The growing demand for data processing has brought severe challenges to computer performance. In order to improve the efficiency of data processing, approximate calculation can be used to replace accurate calculation in imprecision-tolerant applications. In this paper, we propose four approximate full adders with low overhead in term of power, delay and area. The proposed approximate full adders and the approximate full adders existing in the literature are classified into two groups according to their error distances. Simulation results show that the overhead of the proposed approximate full adders in each group is lower than that of the existing approximate full adders. Simulation results also show that, in the first group, the proposed approximate full adders can reduce Power-Area-Delay Product (PADP) by 61.83%, power consumption by 54.15%, area by 44.67%, and delay by 22.78% on average; in the second group, the proposed approximate full adders can reduce PADP by 97.01%, power consumption by 93.43%, area by 24.98%, and delay by 36.14% on average compared with the existing approximate full adders.