In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input Celements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively. CCS CONCEPTS• Hardware → Circuit hardening; Latch design; Transient errors and upsets; Fault tolerance.

The growing demand for data processing has brought severe challenges to computer performance. In order to improve the efficiency of data processing, approximate calculation can be used to replace accurate calculation in imprecision-tolerant applications. In this paper, we propose four approximate full adders with low overhead in term of power, delay and area. The proposed approximate full adders and the approximate full adders existing in the literature are classified into two groups according to their error distances. Simulation results show that the overhead of the proposed approximate full adders in each group is lower than that of the existing approximate full adders. Simulation results also show that, in the first group, the proposed approximate full adders can reduce Power-Area-Delay Product (PADP) by 61.83%, power consumption by 54.15%, area by 44.67%, and delay by 22.78% on average; in the second group, the proposed approximate full adders can reduce PADP by 97.01%, power consumption by 93.43%, area by 24.98%, and delay by 36.14% on average compared with the existing approximate full adders.