Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Repossi, Matteo; Eyssa, W.; Vecchi, Federico; Arcioni, P.; Svelto, F.

doi:10.1109/jssc.2009.2023277

Cited by 53 publications

(13 citation statements)

References 27 publications

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“…The transmission line has a large impact on the accuracy, the area and the power consumption and therefore should be designed carefully. The transmission line can be implemented as a regular differential transmission line or as a slow-wave transmission line [5], [6]. Slow-wave transmission lines are typically made by putting small transversal strips under a pair of wires.…”

Section: Transmission Line Designmentioning

confidence: 99%

Design of a frequency reference based on a PVT-independent transmission line delay

Roose

Smedt

Volkaerts

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper proposes a novel integrated oscillator topology based on a transmission line. The frequency is extracted from the delay of the transmission line, which is intrinsically independent of temperature and supply variations. The architecture for the oscillator, guidelines for the design of the transmission line as well as the different building blocks are presented. The architecture is based on a phase-locked loop topology. The transmission line used has a 509 ps delay, an area of 2.26 mm 2 and a 4.38 dB power loss. The effect of process variations on the transmission line is extensively investigated. A digital driver using CMOS inverters and an analog driver based on an OTA are proposed. Both have a good stability over temperature. The Gilbert cell is proposed as a detector at the output of the transmission line and the corresponding design considerations are shown. Closed loop simulations show fast locking, a variation of 8.3‰ between-10 • C and 85 • C and a variation of 3.7‰ for Vdd ± 10%.

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Section: Transmission Line Designmentioning

confidence: 99%

Design of a frequency reference based on a PVT-independent transmission line delay

Roose

Smedt

Volkaerts

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…However, the transmission line structures commonly used in CMOS technologies including thin-film microstrip line (TFMS) [16] and grounded coplanar waveguide (GCPW) [17], both feature a perfect isolation to the lossy substrate. The electric field is well confined within the signal line and ground, and therefore the characteristic can be predicted accurately by EM simulation softwares.…”

Section: Passive Components Modelingmentioning

confidence: 99%

A model inaccuracy aware design methodology of millimeter-wave CMOS tuned amplifiers

Shin

Dawn

Yeh

et al. 2011

WAMICON 2011 Conference Proceedings

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This paper presents a systematic design methodology of millimeter wave (mm-wave) CMOS tuned amplifier which, for the first time to the best of authors' knowledge, takes the model inaccuracy at mm-wave frequencies into design consideration. Millimeter-wave models for both passive and active components are developed based on the standard foundry provided models with extra critical variation components which represent modeling uncertainties. The proposed model is verified through a comparison with the measured results of the test structures. The design methodology of tolerating the modeling uncertainties is demonstrated by a design example of a 65nm CMOS 57-64 GHz low noise amplifier, which has a 20 dB gain and a minimum 5 dB noise figure with 26 mA current consumption under 1 V supply.Index Terms -millimeter-wave (mmW), CMOS, tunedamplifier, low noise amplifier (LNA).

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“…A few complications arise, including coupling between different TL sections and the effects of bends, in addition to loss, dispersion, and silicon substrate effects. Potential parasitic coupling issues [20] enlist the use of on-chip coplanar waveguide (CPW) since CPWs usually have broader operating frequency range with less loss and less dispersion [21] when compared with microstrip lines. Furthermore, CPWs are often a standard device component in advanced CMOS technologies.…”

Section: Properties Of Periodically Loaded On-chip Transmission Linesmentioning

confidence: 99%

A high-speed sample-and-hold circuit based on CMOS transmission lines

Wang

Gao

et al. 2010

Analog Integr Circ Sig Process

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We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 lm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of *50 ps width with *17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Gigasample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.

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Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Cited by 53 publications

References 27 publications

Design of a frequency reference based on a PVT-independent transmission line delay

Design of a frequency reference based on a PVT-independent transmission line delay

A model inaccuracy aware design methodology of millimeter-wave CMOS tuned amplifiers

A high-speed sample-and-hold circuit based on CMOS transmission lines

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