Design of Low Noise and Low Power LDO for Sensor Application

Sunil, Bisnath; Kulkarni, N.; Pradeep, Pradeep; Praveen, P.; Singh, Bhoopendra; Chippalkatti, Vinod

doi:10.1109/icstcee49637.2020.9276929

Cited by 3 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When the LDO is in the light load state, it is necessary to shut down the error amplifier and other circuits, so that the circuit is in an ultra-low power consumption state to achieve the purpose of energy saving [8] . As shown in Figure 4, the light and heavy load detection circuit is used to determine whether the circuit is loaded by detecting the load current.…”

Section: Light and Heavy Load Detection Circuitmentioning

confidence: 99%

Low power consumption and fast response of low dropout regulator design

Wei,

Huang,

Wang

2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

A low power consumption and fast response low voltage difference linear regulator circuit is designed for on-chip SOC circuit to achieve low power consumption, fast response, and high stability. The internal design mainly includes a low power bandgap reference circuit, a light and heavy load detection circuit, and a transient enhancement circuit. The circuit is designed with 0.35 μm BCD technology, and the layout design is completed. The VIN is from 2.5 V to 5 V, the VOUT from 2.5 V to 3.3 V, and the maximum load is 250 mA. The simulation results show that the static current is 2.6 μA at normal temperature with no load. When the load jumps, the overshoot is 44 mV and the recovery time is 52 μs, meeting the design requirements of low power consumption and fast response.

show abstract

Section: Light and Heavy Load Detection Circuitmentioning

confidence: 99%

Low power consumption and fast response of low dropout regulator design

Wei,

Huang,

Wang

2024

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

“…In the traditional LDO circuit, the noise mainly comes from the bandgap reference circuit and the error amplifier circuit, in which the bandgap reference is the main noise source [5] .…”

Section: Noise Analysismentioning

confidence: 99%

Design of LDO circuit with low noise and high PSRR

Li,

Huang,

Yao

2024

Fourth International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024)

View full text Add to dashboard Cite

“…An increasing number of applications require a low-noise LDO to suppress the output voltage ripple and noise [11,12]. The traditional LDO structure has some limitations in low-noise design.…”

Section: Introductionmentioning

confidence: 99%

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

et al. 2021

View full text Add to dashboard Cite

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

show abstract

Design of Low Noise and Low Power LDO for Sensor Application

Cited by 3 publications

References 4 publications

Low power consumption and fast response of low dropout regulator design

Low power consumption and fast response of low dropout regulator design

Design of LDO circuit with low noise and high PSRR

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Contact Info

Product

Resources

About