Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

Bhumireddy, V. R.; Shaik, Khaja Ahmad; Amara, Ayed Ben; Sen, Samita; Parikh, Chetan D.; Nagchoudhuri, D.; Ioinovici, A.

doi:10.1109/circuitsandsystems.2013.6671626

Cited by 9 publications

(4 citation statements)

References 7 publications

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“…For each sub-band, n, we wish to discriminate between the two hypotheses H 0,n and H 1,n where the first assumes that the primary signal is not in band and the second assumes that the primary user is present. Using the average energy decision statistic, one can define these hypotheses under the assumption of infinite ADC precision as given by (4).…”

Section: A Non-quantized Exact System Performancementioning

confidence: 99%

“…For example, the recent 12-bit ADC 12D1600QML-SP from Texas Instruments can process 3.2GSamples/sec at a power consumption of 3.88Watts. On the other hand, a single high speed comparator (1-bit ADC) with the same operating frequency is designed to dissipate 20µWatts [4]. Further, the complexity is extremely reduced as automatic gain control is not required for these systems.…”

Section: Introductionmentioning

confidence: 99%

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Low Power Wideband Sensing for One-Bit Quantized Cognitive Radio Systems

Ali

Hamouda

2016

IEEE Wireless Commun. Lett.

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We proposes an ultra low power wideband spectrum sensing architecture by utilizing a one-bit quantization at the cognitive radio (CR) receiver. The impact of this aggressive quantization is quantified and it is shown that the proposed method is robust to low signal-to-noise ratios (SNR). We derive closedform expressions for both false alarm and detection probabilities. The sensing performance and the analytical results are assessed through comparisons with respective results from computer simulations.The results indicate that the proposed method provides significant saving in power, complexity, and sensing period on the account of an acceptable range of performance degradation. Index TermsCognitive radio, low power, one-bit quantizer, wideband sensing.

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Section: A Non-quantized Exact System Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Power Wideband Sensing for One-Bit Quantized Cognitive Radio Systems

Ali

Hamouda

2016

IEEE Wireless Commun. Lett.

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“…On the other hand, this FVF design consumes more power. In 2013, Bhumireddy et al introduced a novel latch-based comparator for successive approximation ADC with sub-32 nm double gate MOSFETs (DG-MOSFET) [ 19 ]. In this design, the regeneration time of the latch is enhanced by employing an extra positive feedback, which in turn increases the offset voltage and the propagation delay.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed and Low-Offset Dynamic Latch Comparator

Rahman

Reaz

Yin

et al. 2014

The Scientific World Journal

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Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.

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“…(a) Sense amplifier based on regenerative latch[Song et al 1995;Bhumireddy et al 2013] (b) multilevel sensing scheme using the sense amplifier in (a).…”

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confidence: 99%

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

Venkatesan

Sharad

Roy

et al. 2015

J. Emerg. Technol. Comput. Syst.

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Spintronic memories are considered to be promising candidates for future on-chip memories due to their high density, nonvolatility, and near-zero leakage. However, they also face challenges such as high write energy and latency and limited read speed due to single-ended sensing. Further, the conflicting requirements of read and write operations lead to stringent design constraints that severely compromises their benefits.Recently, domain wall memory was proposed as a spintronic memory that has a potential for very high density by storing multiple bits in the domains of a ferromagnetic nanowire. While reliable operation of DWM memory with multiple domains faces many challenges, single-bit cells that utilize domain wall motion for writes have been experimentally demonstrated [Fukami et al. 2009]. This bit-cell, which we refer to as Domain Wall Memory with Shift-based Write (DWM-SW), achieves improved write efficiency and features decoupled read-write paths, enabling independent optimizations of read and write operations. However, these benefits are achieved at the cost of sacrificing the original goal of improved density. In this work, we explore multilevel storage as a new direction to enhance the density benefits of DWM-SW. At the device level, we propose a new device-multilevel DWM with shift-based write (ML-DWM-SW)-that is capable of storing 2 bits in a single device. At the circuit level, we propose a ML-DWM-SW based bit-cell design and layout. The ML-DWM-SW bit-cell incurs no additional area overhead compared to the DWM-SW bit-cell despite storing an additional bit, thereby achieving roughly twice the density. However, it requires a two-step write operation and has data-dependent read and write energies, which pose unique challenges. To address these issues, we propose suitable architectural optimizations: (i) intra-word interleaving and (ii) bit encoding. We design "all-spin" cache architectures using the proposed ML-DWM-SW bit-cell for both general purpose processors as well as general purpose graphics processing units (GPGPUs). We perform an iso-capacity replacement of SRAM with spintronic memories and study the energy and area benefits at iso-performance conditions. For general purpose processors, the ML-DWM-SW cache achieves 10X reduction in energy and 4.4X reduction in cache area compared to an SRAM cache and 2X and 1.7X reduction in energy and area, respectively, compared to an STT-MRAM cache. For GPGPUs, the ML-DWM-SW cache achieves 5.3X reduction in energy and 3.6X area reduction compared to SRAM and 3.5X energy reduction and 1.9X area reduction compared to STT-MRAM. . 2015. Energy-efficient all-spin cache hierarchy using shift-based writes and multilevel storage. ACM

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Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

Cited by 9 publications

References 7 publications

Low Power Wideband Sensing for One-Bit Quantized Cognitive Radio Systems

Low Power Wideband Sensing for One-Bit Quantized Cognitive Radio Systems

A High-Speed and Low-Offset Dynamic Latch Comparator

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

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