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To achieve 0.5-V high-speed SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), combined with a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V DD /2. The other is a partial activation of a multi-divided open-bitline array without significant area penalty. Layout and postlayout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x6 faster and x14 lower power than the counterpart 6T-cell array, suggesting a possibility of a 540-ps cycle time at 0.5 V. Keywords-0.5-V 5T-cell SRAM array, multi-divided open bitlines, boosted word-line, and mid-point sensing.