Design of low‐power high‐speed CNFET 1‐trit unbalanced ternary multiplier

Abstract

Existing two‐level binary logic and MOSFET (metal oxide semiconductor field effect transistor) technology have limitations. To overcome the limitations, three levels ternary logic with CNFET (carbon nanotube field effect transistor) technology is introduced. In this paper, the 1‐trit ternary multiplier is reconfigured for wide applications using CNFET Stanford model, for low and high die temperature. The proposed design is compared with two existing designs of the multiplier on the basis of power consumption, delay, requirements of the chip area, and other parameters. The proposed design uses a decoder that is a modified version of existing decoders. The role of the modified decoder is to convert ternary signals into binary form. Because of this conversion, analysis and implementation of the circuit become easier along with improvement in power consumption and delay with other parameters at low and high temperature.

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

“…The area of each TSRAM circuit can be calculated by summing the areas of individual transistors in the circuit as mentioned in [67]. Table 7 presents the areas of the investigated TSRAM circuits.…”