Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

Abstract

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

“…The pipelined 8-bit CLA adder has been designed using CDCAL. The adiabatic CLA adder uses two complementary two phase sinusoidal power clock signals [6] as power supply. The sum Si and carry Ci output functions of each stage of the 8-bit CLA adder as represented by…”

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

“…Therefore, decreasing power consumption in battery powered equipment is a crucial objective of low-power VLSI circuit design. For typical CMOS network, the power lost as a consequence of charging and discharging at the node of output's capacitor is estimated as aC V f, L DD 2 [2][3][4][5][6][7][8][9]. Much efforts have been made to reduce power dissipations in conventional CMOS circuits, such as reducing switching activity ( ) a , reducing load capacitance ( ) C , L dropping the applied voltage ( ) V DD and lowering the charging frequency ( ) f .…”

“…ADCL [4] and 2PASCL [5] with 0.3 μm CMOS technology. In addition, extensive analyses were carried out to establish the benefits of the suggested circuit with the Berkeley High Performance Predictive Models (HP_PTM) and the results for basic gates are compared with some of the most recent adiabatic literature, including QSERL [6], 2PADCL [7], CCAL [8], 2PADL [9], DFAL [17][18][19], and A-DSCVL [20]. The schematics for the fundamental inverter circuits are shown in figures 2-9.…”

Low power architecture of logic gates using adiabatic techniques

“…NAND/NOR gate are deisgned based on positive feedback adiabatic logic (PFAL) and two phase clocked adiabatic static CMOS logic (2PASCL) techniques [6]. Two phase adiabatic dynamic logic (2PADL) is used to design a carry lookahead adder which has the advantages of energy efficiency and lower switching power due to the usage of gate overdrive because of this feature it can be used in a variety of low-power very large scale integrated (VLSI) designs [7]. Further, energy efficient different gates are design using various adiabatic approach like CMOS, 2N2P, efficient charge recovery logic (ECRL) and PFAL adiabatic logic for low power applications [8].…”