Design of mixed gates for leakage reduction

As integrated circuit technologies progress to nanoscale, process variations become relatively large and significantly impact circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. In the present scenario, designers are searching for analogue-to-digital converter (ADC) architectures which are nanoscale CMOS processes tolerant. Expectations of the performance of ADCs are continuously increasing along with the progress of digital systems. A process and supply variation tolerant, System-on-Chip (SoC) ready, 1 GS/s, 6-bit flash ADC suitable for integration into nanoscale digital CMOS technologies is presented. The physical design of the ADC has been done using a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit. Baseline post layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC is then subjected to a corner-based methodology of process variation. The results show that process variation causes a maximum variation of 10.5% in the integral nonlinearity (INL) and 5.7% in the differential non-linearity (DNL), with both INL and DNL being less than 0.5 LSB. The 90 nm ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators for the ADC have been designed using the threshold inverting technique. To show technology scalability of the design, the ADC has also been presented using a 45 nm Predictive Technology Models (PTM). At 45 nm, INL ¼ 0.46 LSB, DNL ¼ 0.7 LSB and a sampling rate of 100 MS/s were obtained. The 45 nm ADC consumes a peak power of 45.42 mW, and average power of 8.8 mW.

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“…The subthreshold leakage current in a transistor is represented as follows (Fotty 1997;Sill, You and Timmerman 2007):…”

Section: Power Analysismentioning

confidence: 99%

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

Ghai

Mohanty

Kougianos

2010

International Journal of Electronics

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“…Firstly, we simulated basic logic gates on transistor level with HSpice to demonstrate that shadow transistors can compensate for impaired transistors due to TDDB (presented in section 4.1). Thereto, we used modified predictive transistor models from a 65 nm technology ─ called L-V t /To [16]. Furthermore, basic logic gates were characterized in terms of power consumption and delay for the various cases that one or several shadow transistors can be inserted.…”

Section: Setupmentioning

confidence: 99%

“…That is, if we apply devices with thicker gate oxide, the expected lifetime increases as well. Fortunately, the chosen transistor models also include H-V t /To transistors for this case [16]. Such transistors have thicker gate oxide and higher threshold voltage, and thus, they are slower and exhibit less leakage currents compared to the standard L-V t /To types.…”

Section: Applying Dual-v Tmentioning

confidence: 99%

Encountering gate oxide breakdown with shadow transistors to increase reliability

Cornelius

Sill

Sämrow

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Traditionally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards operational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does improve system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an algorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transistors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark circuits and prove the combined approach successful. The enhanced designs were on average 41.8 % more reliable compared to the initial designs in respect of TDDB at the price of moderately increased power consumption and delay.

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“…This power dissipation depends on loading conditions and not the device features. The subthreshold leakage of a nano-CMOS device is calculated by the following expression [Sill et al 2007].…”

Section: Models For Power and Delay Calculation Of The Ulsmentioning

confidence: 99%

“…The delay of a CMOS circuit is approximately calculated using the follow expression [Sill et al 2007]. We have where γ is a technology-dependant constant, μ is the electron surface mobility, and α is the velocity saturation index, which varies from 1.4 to 2 for nano-CMOS, gate dielectric constant of the gate oxide, L eff is the effective channel length, and W eff is the effective width of the transistors.…”

Section: Models For Power and Delay Calculation Of The Ulsmentioning

confidence: 99%

Uls

Mohanty

Pradhan

2008

J. Emerg. Technol. Comput. Syst.

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Power dissipation is a major bottleneck for emerging applications, such as implantable systems, digital cameras, and multimedia processors. Each of these applications is essentially designed as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These AMS-SoCs are typically operated from a single power-supply source which is a battery providing a constant supply voltage. In order to reduce power dissipation of the AMS-SoCs, multiple-supply voltage and/or variable-supply voltage is used as an attractive low-power design approach. In the multiple-/variable-supply voltage AMSSoCs the use of a DC-to-DC voltage-level shifter is critical. The voltage-level shifter is an overhead when its own power dissipation is high. In this article a new DC-to-DC voltage-level shifter is introduced that performs level-up shifting, level-down shifting, and blocking of voltages and is called Universal Level Shifter (ULS). The ULS is a unique component that reduces dynamic power and leakage of the AMS-SoCs while facilitating their reconfigurability. The system-level architectures for three AMS-SoCs, such as Drug Delivery Nano-Electro-Mechanical-System (DDNEMS), Secure Digital Camera (SDC), and Net-centric Multimedia Processor (NMP) are introduced to demonstrate the use the ULS for system-level power management. The article presents a design flow and an algorithm for optimal design of the ULS using a dual-V th high-κ technique for efficient realization of ULS. A prototype ULS is presented for 32nm nano-CMOS technology node. The robustness of the ULS design is examined by performing three types of analysis, such as parametric, load, and power. It is observed that the ULS produces a stable output for voltages as low as 0.35V and loads varying from 50 f F to 120 f F. The average power dissipation of the ULS with a 82 f F capacitive load is 5μW . (AMS-SoC), low-power design, nanoscale CMOS, system-level power management, DC-to-DC voltage-level shifter, dual-threshold voltage, high-κ/metal-gate nano-CMOS ACM Reference Format:Mohanty, S. P. and Pradhan, D. K. 2010. ULS: A dual-V th /high-κ nano-CMOS universal level shifter for system-level power management. ACM

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Design of mixed gates for leakage reduction

Cited by 12 publications

References 10 publications

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

Encountering gate oxide breakdown with shadow transistors to increase reliability

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