Design of multicore digitally controlled oscillator in 65 nm CMOS technology

Mačaitis, Vytautas; Navickas, Romualdas

doi:10.1109/estream.2017.7950310

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Due to the limited number of IC package pads, only two divider outputs (division by 64 and 256) were connected to be measured externally. In order to check the frequency divider separately, it was included as an independent block but with different division ratios (division by 16 and 32) [6].…”

Section: Design Of the Lc Dco And Frequency Dividermentioning

confidence: 99%

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Mačaitis

Navickas

2019

Electronics

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This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

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Section: Design Of the Lc Dco And Frequency Dividermentioning

confidence: 99%

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Mačaitis

Navickas

2019

Electronics

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“…Taip pat kuriami ir tiriami pagaminto taikant 0,18 µm technologiją įtampa valdomo generatoriaus bei pagaminto taikant 0,13 µm technologiją skaitmeninių būdu valdomo generatoriaus integriniai grandynai. Skyriaus tematika paskelbti penki autoriaus straipsniai (Macaitis, Jurgo, Charlamov, & Barzdenas, 2016;Macaitis & Navickas, 2017c, 2017a.…”

Section: Lc įTampa Ir Skaitmeniniu Būdu Valdomų Generatorių Ir Papildomų Blokų Projektavimas Ir Tyrimasunclassified

“…Suprojektuotas integrinis grandynas sudarytas iš dviejų dalių: LC-SVG išėjimo signalo dažnio generavimo ir dažnio daliklio grandinės bei nepriklausomos dažnio daliklio grandinės. Dėl riboto integrinio grandyno korpuso išvadų skaičiaus, tik du daliklio išėjimai (dalyba iš 64 ir 256) buvo prijungti tolimesniam testavimui (Macaitis & Navickas, 2017c).…”

Section: Lc Skaitmeniniu Būdu Valdomo Generatoriaus Projektavimas Ir Tyrimas Taikant 013 µM Technologijąunclassified

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

Mačaitis¹

2019

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Disertacija rengta 2015-2019 metais Valstybiniame mokslinių tyrimų institute Fizinių ir technologijos mokslų centre. Vadovas prof. habil. dr. Romualdas NAVICKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Vilniaus Gedimino technikos universiteto elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo taryba: Pirmininkas prof. dr. Šarūnas PAULIKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Nariai: dr. Alvydas LISAUSKAS (Lenkijos mokslų akademijos Aukšto slėgio fizikos institutas, fizika -N 002), dr. Vitalij NOVICKIJ (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001), dr. Česlovas ŠIMKEVIČIUS (Valstybinis mokslinių tyrimų institutas Fizinių ir technologijos mokslų centras, elektros ir elektronikos inžinerija -T 001), prof. dr. Algimantas VALINEVIČIUS (Kauno technologijos universitetas, elektros ir elektronikos inžinerija -T 001). Disertacija bus ginama viešame Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo tarybos posėdyje 2019 m. lapkričio 8 d. 13 val. Valstybinio mokslinių tyrimų instituto Fizinių ir technologijos mokslų centro posėdžių salėje D401.

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“…Staszewski 7 proposed the first LC-DCO operating at radiofrequency (RF) frequency based on the 0.13-μm CMOS process and realized a phase noise of À112 dBc/Hz at 500 kHz offset by cascading a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). Reduced phase noise is obtained by using multi-core DCO, [8][9][10] for instance, Tomasin 8 designed an eight-core DCO covering a frequency tuning range of 27% with an average resolution of 6 MHz and a phase noise of À126 dBc/Hz at 1 MHz offset. However, the use of multi-core DCO design occupies a large chip area and increases power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

Zou

Cheng

et al. 2023

Circuit Theory & Apps

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SummaryA high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2.

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Design of multicore digitally controlled oscillator in 65 nm CMOS technology

Cited by 5 publications

References 6 publications

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

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