Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

Leary, Glenn; Srinivasan, K.; Mehta, K.; Chatha, Karam S.

doi:10.1109/tvlsi.2008.2011205

Cited by 66 publications

(55 citation statements)

References 18 publications

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“…This is done usually by either dedicated Synchronizer library cells (typically for single bit or small set of signals) or using an ASYNC FIFO (for multiple bits and wide data-buses) [18,16]. Existing NoC topology aproaches such as [7,10,9,12] generate a network topology but do not assign clock-domains (or frequencies) to their constituent routers. This job is left to the designer to do by visual inspection and taking into consideration the clock domains of the various cores (Masters and Slaves) which are known beforehand.…”

Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

“…The optimization of CDC in a NoC requires for the modeling of a CDC cost and its inclusion in the optimization function of the SA [10,9] or GA [12] algorithms of the topology generation tools. This cost can be measured as the number of CDCs itself or as a secondary objective such as number of flops needed in the fabric.…”

Section: The Router Coloring Problemmentioning

confidence: 99%

“…The application specific network topology generation problem is a variation of the generalized steiner forest problem [6], which is known to be NP hard. Researchers have usually utilized linear-programming (LP) [7,8], simulated-annealing (SA) [9,10] or heuristic optimization [11,12,13,14,15] based techniques to solve the topology generation problem. Early approaches [13,8] focused on minimizing the dual objectives of area and power by using cost functions expressed as weighted linear combinations of area and power.…”

Section: Introductionmentioning

confidence: 99%

“…Early approaches [13,8] focused on minimizing the dual objectives of area and power by using cost functions expressed as weighted linear combinations of area and power. More recent approaches [7,12,9,15] have begun incorporating increasing levels of physical information such as estimates of wire-length and floorplan area, with [9] integrating physical floorplanning and NoC topology generation to make use of more realistic interconnect information. While cost and optimization functions have become more complex by adding multiple objectives, no existing work explicitly looks to optimize for CDC during topology generation.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Minimizing clock domain crossing in Network on Chip interconnect

Kulkarni

Gupta

Beraha

2014

Fifteenth International Symposium on Quality Electronic Design

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Abstract-Network-on-Chip (NoC) architectures have been widely adopted as the preferred solution to the communication challenges of System-on-Chip (SoC) design in the nanoscale regime. SoC designs often incorporate custom NoC architectures that do not conform to regular topologies. This requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. Hence automated topology generation tools optimize for mutiple objectives like power and area to synthesize a NoC topology that meets these communication constraints. Clock-Domain-Crossings (CDCs) is an important consideration in fabric design that gets ignored in existing topology tools. CDCs add to latency and area, while also increasing verification and implementation effort. In this paper we propose a method to model and optimize the clock-domain-crossings (CDC) during NoC topology generation and prove that the underlying problem is NP-hard. We present and compare multiple approaches to model the CDC cost, including a novel fast heuristic. When applied within an existing topology generation tool our approach results in a 5% − 39% reduction in flop count of the resulting interconnect while still satisfying the original communication/performance constraints.

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Section: Cdc In Network On Chip Interconnectmentioning

confidence: 99%

Section: The Router Coloring Problemmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Minimizing clock domain crossing in Network on Chip interconnect

Kulkarni

Gupta

Beraha

2014

Fifteenth International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…Both topologies require global wires which go across one or more processors. Mapping arbitrary non-regular topologies to a 2D floorplan is an NP-hard optimization problem [3].…”

Section: Introductionmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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NoC Modeling and Topology Exploration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

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This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints. IntroductionWith the advent of chip multi-processors (CMP) and multi-core systems-on-chip (SoC), the network-on-chip (NoC) paradigm has been proposed as a viable solution to the problem of connecting the continuously increasing number of processing cores that are integrated on a single die. The communication problem is expected to become far more important with the demand for higher processing power posed by the majority of application domains and the technology scaling.Even though the NoC-based communication scheme introduces architectural scalability and performance enhancement, as already discussed in Chap. 1, however, careful design is absolutely required in order to achieve these gains. In this chapter, we discuss a number of architectural issues related to widely accepted NoC topologies. Additionally, the available academic and commercial solutions for topology modeling and synthesis are presented, whereas the main features/limitations for each of them are highlighted. In order to quantify the efficiency for each architectural selection, appropriate benchmarks are also required. For this purpose, throughout the second chapter we also introduce a number of typical traffic models employed for the scope of evaluating NoC architectures. Since the design, as well as the quantification of these NoC parameters are rather complex tasks, which cannot be easily performed without the usage of dedicated software tools, a number of frameworks are also introduced.K. Tatas et al., Designing 2D and 3D Network-on-Chip Architectures,

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Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

Cited by 66 publications

References 18 publications

Minimizing clock domain crossing in Network on Chip interconnect

Minimizing clock domain crossing in Network on Chip interconnect

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

NoC Modeling and Topology Exploration

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