Design of Power Efficient Posit Multiplier

Zhang, Hao; Ko, Seok‐Bum

doi:10.1109/tcsii.2020.2980531

Cited by 33 publications

(17 citation statements)

References 7 publications

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“…The designs presented in [2], [4], and [7] are open-source but do not synthesize for exponent size zero while the design presented in [5] is not open-source. A power-efficient posit multiplier is presented in [12]. The authors in [12] present a scheme where they divide the fraction part of the multiplier into several chunks and use them efficiently resulting in 16% power efficiency over the base-line implementation.…”

Section: Related Workmentioning

confidence: 99%

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Brightening the Optical Flow through Posit Arithmetic

Saxena

Reddy

Neudorfer

et al. 2021

2021 22nd International Symposium on Quality Electronic Design (ISQED)

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As new technologies are invented, their commercial viability needs to be carefully examined along with their technical merits and demerits. The posit TM data format, proposed as a drop-in replacement for IEEE 754 TM float format, is one such invention that requires extensive theoretical and experimental study to identify products that can benefit from the advantages of posits for specific market segments. In this paper, we present an extensive empirical study of posit-based arithmetic vis-à-vis IEEE 754 compliant arithmetic for the optical flow estimation method called Lucas-Kanade (LuKa). First, we use SoftPosit and SoftFloat format emulators to perform an empirical error analysis of the LuKa method. Our study shows that the average error in LuKa with SoftPosit is an order of magnitude lower than LuKa with SoftFloat. We then present the integration of the hardware implementation of a posit adder and multiplier in a RISC-V open-source platform. We make several recommendations, along with the analysis of LuKa in the RISC-V context, for future generation platforms incorporating posit arithmetic units.

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Section: Related Workmentioning

confidence: 99%

“…A power-efficient posit multiplier is presented in [12]. The authors in [12] present a scheme where they divide the fraction part of the multiplier into several chunks and use them efficiently resulting in 16% power efficiency over the base-line implementation.…”

Section: Related Workmentioning

confidence: 99%

Brightening the Optical Flow through Posit Arithmetic

Saxena

Reddy

Neudorfer

et al. 2021

2021 22nd International Symposium on Quality Electronic Design (ISQED)

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“…In order to use posits on a conventional processor, we developed for the Julia programming language (Bezanson et al, 2017) the posit emulator SoftPosit.jl (Klöwer & Giordano, 2019) as bindings for the C-based library SoftPosit (Leong, 2020). A standardized posit processor is not yet available, but current research focuses on hardware implementations (Chaurasiya et al, 2018;Chen et al, 2018;Glaser et al, 2017;van Dam et al, 2019;Zhang & Ko, 2020…”

Section: The Posit Number Formatmentioning

confidence: 99%

Number Formats, Error Mitigation, and Scope for 16‐Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

Klöwer

Dueben

Palmer

2020

J Adv Model Earth Syst

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The need for high-precision calculations with 64-bit or 32-bit floating-point arithmetic for weather and climate models is questioned. Lower-precision numbers can accelerate simulations and are increasingly supported by modern computing hardware. This paper investigates the potential of 16-bit arithmetic when applied within a shallow water model that serves as a medium complexity weather or climate application. There are several 16-bit number formats that can potentially be used (IEEE half precision, BFloat16, posits, integer, and fixed-point). It is evident that a simple change to 16-bit arithmetic will not be possible for complex weather and climate applications as it will degrade model results by intolerable rounding errors that cause a stalling of model dynamics or model instabilities. However, if the posit number format is used as an alternative to the standard floating-point numbers, the model degradation can be significantly reduced. Furthermore, mitigation methods, such as rescaling, reordering, and mixed precision, are available to make model simulations resilient against a precision reduction. If mitigation methods are applied, 16-bit floating-point arithmetic can be used successfully within the shallow water model. The results show the potential of 16-bit formats for at least parts of complex weather and climate models where rounding errors would be entirely masked by initial condition, model, or discretization error. Plain Language Summary 64-bit floating-point numbers are the standard number format for scientific computing in fluid dynamics, which allows for very precise calculations with negligible rounding errors. The need for calculations at this precision level has been questioned for weather and climate models, as errors are caused primarily by insufficient observations or deficiencies of the models themselves. Reducing numerical precision can accelerate simulations and low-precision number formats are increasingly supported by modern computers. This paper investigates the potential of low numerical precision with numbers that only use 16 bit of information, when applied within simulations of weather and climate. The different number formats are applied in a two-dimensional oceanic or atmospheric circulation model. There are several 16-bit number formats that can potentially be used, all of which have considerably larger rounding errors than the standard 64-bit numbers. A simple change to 16 bits for all calculations will not be possible as it will degrade simulation results. However, if mitigation methods are applied, 16-bit calculations can be used successfully within the applications of this paper. The results show the potential of 16-bit number formats for at least parts of complex weather and climate models.

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“…This format has been proven to match single precision accuracy performance with only 16 bits used for the representation [9,12,16,17,24]. Furthermore, the first hardware implementations of this novel type are very promising in terms of energy consumption and area occupation [10,20,28].…”

Section: Introductionmentioning

confidence: 99%

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Cococcioni

Rossi

Ruffaldi³

et al. 2021

Neural Comput & Applic

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With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

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Design of Power Efficient Posit Multiplier

Cited by 33 publications

References 7 publications

Brightening the Optical Flow through Posit Arithmetic

Brightening the Optical Flow through Posit Arithmetic

Number Formats, Error Mitigation, and Scope for 16‐Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

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