Design of Q-enhanced Class-C VCO with robust start-up and high oscillation stability

Tian, Mi; Wang, Zhigong; Xu, Jing; Zhang, Changchun

doi:10.1587/elex.11.20140982

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…However, analog AAC loops inject extra noise so that large current is required to reduce the injected noise [13]. Meanwhile, analog AAC loops suffer from stability problems especially when they are adopted in Class-C VCOs with start-up loops [17,18,19,20,21]. Therefore, digital AAC techniques have been proposed to eliminate the noise and stability problems [22,23].…”

Section: Introductionmentioning

confidence: 99%

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Li¹,

Wang²,

Wang³

et al. 2021

IEICE Electron. Express

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This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm 2 . By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

show abstract

Section: Introductionmentioning

confidence: 99%

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Li¹,

Wang²,

Wang³

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Conventional Class-AB oscillator has lower dc-RF power conversion efficiency than Class-C oscillator because of the overlapping of drain current and voltage in switching devices. Conventional Class-C oscillator lowers the gate bias to reduce the dc current; therefore, the dc-RF power conversion efficiency improves, the popular Class-C VCO uses either dynamic source bias or dynamic gate bias [1][2][3] to force an oscillator operate in the Class-C mode. The VCO initially oscillates in Class-AB mode to guarantee VCO oscillation, and then switches to Class-C mode achieving low power in the steady state.…”

mentioning

confidence: 99%

Low‐phase noise Class‐C VCO with dynamic body bias

Jang

Wang

2017

Electron. lett.

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A 2.5 GHz Class-C voltage-controlled oscillator (VCO) with dynamic back-gate-biased MOSFET is proposed. A dynamic gate biasing circuit is used to reduce power consumption by switching N-type MOS from initial Class-AB to Class-C operation in steady state. Moreover, the VCO uses dynamic back-gate bias to reduce threshold voltage of switching MOSFET during the start-up oscillation. The Class-C differential VCO is implemented in TSMC 0.18 μm bipolarcomplementary-metal-oxide-semiconductor (BiCMOS) process. The measured phase noise is −124.8 dBc/Hz at 1 MHz offset frequency from 2.48 GHz carrier while consuming 2.64 mW power from a 0.8 V supply. Tuning range of VCO is 0.72 GHz, from 2.48 to 3.3 GHz, whereas the control voltage was tuned from 0 to 2 V. The VCO occupies a chip area of 446 × 840 μm 2 and provides a figure of merit of −197.55 dBc/Hz.

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Low‐power three‐path inductor class‐C VCO without any dynamic bias circuit

Jang

Lin

2017

Electron. lett.

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A 2.48 GHz class-C voltage controlled oscillator (VCO) without any dynamic back bias circuit is presented. The VCO uses three-path high Q-factor inductor as the low loss resonator and class-C crosscoupled nMOSFET pairs for high dc/RF conversion efficiency and direct cross-coupled pMOSFET for dc current reuse. At the supply voltage of 1.2 V, the core power consumption is 0.24 mW. The phase noise of the VCO is −124 dBc/Hz and the VCO figure of merit is −197.0 dBc/Hz. The VCO was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process and occupies a die area of 0.799 × 0.809 mm 2 .

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Design of Q-enhanced Class-C VCO with robust start-up and high oscillation stability

Cited by 5 publications

References 9 publications

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Low‐phase noise Class‐C VCO with dynamic body bias

Low‐power three‐path inductor class‐C VCO without any dynamic bias circuit

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