Design of resolution adaptive TIQ flash ADC using AMS 0.35 µm technology

Rajashekar, G.; Bhat, M. S.

doi:10.1504/ijict.2009.026426

Cited by 7 publications

(10 citation statements)

References 4 publications

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“…(18) Proof. Replacing σ 2 yi with σ 2 xi (c i = σ 2 xi ) in (37) and following the same steps in the proof of Proposition 1 in Appendix A, we obtain (42). Then, (18) is obtained by putting z i = 2 −2bi , z = 2 −2b and c i = σ 2 xi into (42).…”

Section: B Revised Mmsqe Bit Allocationmentioning

confidence: 99%

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

Choi

Evans

Gatherer

2017

IEEE Trans. Signal Process.

126

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In this paper, we propose a hybrid analog-digital beamforming architecture with resolution-adaptive ADCs for millimeter wave (mmWave) receivers with large antenna arrays. We adopt array response vectors for the analog combiners and derive ADC bit-allocation (BA) solutions in closed form. The BA solutions reveal that the optimal number of ADC bits is logarithmically proportional to the RF chain's signal-to-noise ratio raised to the 1/3 power. Using the solutions, two proposed BA algorithms minimize the mean square quantization error of received analog signals under a total ADC power constraint. Contributions of this paper include 1) ADC bit-allocation algorithms to improve communication performance of a hybrid MIMO receiver, 2) approximation of the capacity with the BA algorithm as a function of channels, and 3) a worst-case analysis of the ergodic rate of the proposed MIMO receiver that quantifies system tradeoffs and serves as the lower bound. Simulation results demonstrate that the BA algorithms outperform a fixed-ADC approach in both spectral and energy efficiency, and validate the capacity and ergodic rate formula. For a power constraint equivalent to that of fixed 4-bit ADCs, the revised BA algorithm makes the quantization error negligible while achieving 22% better energy efficiency. Having negligible quantization error allows existing state-of-the-art digital beamformers to be readily applied to the proposed system.

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Section: B Revised Mmsqe Bit Allocationmentioning

confidence: 99%

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

Choi

Evans

Gatherer

2017

IEEE Trans. Signal Process.

126

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“…Meanwhile, to get the CMOS transistor channel L of each first inverter refers to the mathematical expression of the threshold voltage (V th ) of any quantized sub-unit can be derived approximately as Eq. (2) [13,14].…”

Section: Tiq Comparatormentioning

confidence: 99%

A low power serial output flash ADC in 0,18 µm CMOS process

Reaz

Amin

et al. 2015

Teh. vjesn.

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Original scientific paper This paper proposes a simple design of a flash analog-to-digital converter (ADC) in 0,18 μm CMOS technology. This ADC is expected to be used within a temperature sensor, which provides analog data output having a range of 360 mV to 560 mV. This system consists of three main blocks: the threshold inverter quantization (TIQ)-comparator, encoder and parallel input serial output (PISO) register. The design goal is to get a flash ADC with low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length, for finding out the threshold voltage difference of the inverter each on the TIQ comparator. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844,48 × 764,77 µm 2 and the power dissipation is 0,162 µW with 1,6 V supply voltage. Keywords: CMOS, Comparator, Flash ADC, Temperature Sensor Serijski izlazni impulsni ADC male snage u 0,18 µm CMOS postupkuIzvorni znanstveni članak U radu se predlaže jednostavan projekt impulsno analogno-digitalnog pretvarača (ADC) u 0,18 μm CMOS tehnologiji. Taj bi se pretvarač trebao koristiti u senzoru temperature, koji daje izlaz analognih podataka u rasponu od 360 mV do 560 mV. Sustav se sastoji od tri glavna bloka: threshold inverter quantization (TIQ) -komparatora, kodnog uređaja (kodera) i parallel input serial output (PISO) registra. Svrha je projekta dobiti impulsni ADC s malim gubitkom energije, malih dimenzija i kompatibilnim sa senzorima temperature. Ovom bi se metodom trebala podesiti dužina svakog kanala tranzistora u svrhu pronalaženja razlike u ulaznom naponu pretvarača na TIQ komparatoru. Projektom se predviđa ulazni raspon od 285 do 600 mV i izlaz rezolucije 6-bita. Površina čipa projektiranog ADC je 844,48 × 764,77 µm 2 a gubitak energije iznosi 0,162 µW uz napajanje od 1,6 V.

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“…Several flash or flash-based ADCs use inverter-based comparators to obtain high speeds and low power consumption. However, the variation among inverterbased comparators limits flash ADC resolution [3]. A pipelined ADC uses several inverter-based comparators, but the measured result only shows a subcircuit with one inverter-based comparator [4].…”

Section: Introductionmentioning

confidence: 99%

An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation

Jen

Lin

2016

IEICE Trans. Electron.

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This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-μm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181 fJ/Conv.-step at a 25 kS/s sampling rate when the supply voltage V DD is 1.2 V. key words: Analog-to-digital converter, successive approximation register ADC, inverter-based, design automation.

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Design of resolution adaptive TIQ flash ADC using AMS 0.35 µm technology

Cited by 7 publications

References 4 publications

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

Resolution-Adaptive Hybrid MIMO Architectures for Millimeter Wave Communications

A low power serial output flash ADC in 0,18 µm CMOS process

An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation

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