Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}$$ { 2 k , 2 n - 1 , 2 n + 1 , 2 n + 1 - 1 , 2 n - 1 - 1 } (n Even)

Abstract

This paper presents the design methods of residue-to-binary (reverse) converters for the new flexible balanced five-moduli set {2 k , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} for the pairs of positive integers n ≥ 4 (even) and any k > 0, which can provide the exact required dynamic range of the residue number system. This modulus set is the generalisation of the five-moduli set {2 n , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} (n even) with only a single parameter, n. The reverse converter for the new modulus set is the first ever proposed. Synthesis results obtained for the 65 nm technology for all dynamic ranges from 19 to 88 bits have shown that the state-of-the-art converters available for the five-modulus sets with a single parameter n {2 n , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} (n even) and {2 n − 1, 2 n , 2 n + 1, 2 n+1 + 1, 2 n−1 + 1} (n odd) not only introduce from 28 to 40% larger delay but also still consume more area and power than the converters proposed here.

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

“…In this section, the proposed reverse converters have been evaluated and compared with their closest counterparts: [47], and also {2 k , 2 n -1, 2 n +1, 2 n+1 -1, 2 n-1 -1} proposed in [48]. The conversion delay estimation of the proposed converters and other converters in literature are illustrated in Table 3.…”

“…In table 3, dCSA(a) denotes the delay of an a-operand CSA, dCPAm(a) [dCPAp(a)] denotes the delay of an a-bit [(a + 1)-bit] adder mod 2 a − 1 (2 a + 1), whereas dADD(a) is the delay of an a-bit CPA. Delay and area of the proposed reverse converter and other works reported in [46][47][48] are calculated based on full adder and are included in table 4. In order to have fair comparison, delay of modulo 2 k -1 and 2 k +1 adder reported in [42] with 2k and 4(k+1) delay of full adder and ripple carry adder for CPA are considered.…”

“…Nevertheless, as the number of modules increases, the selected moduli set results in a more complex reverse converter. The studies [47] and [48] present efficient reverse converters for five moduli set {2 n -1, 2 n , 2 n +1, 2 n+1 +1, 2 n-1 +1} and {2 n -1, 2 k , 2 n +1, 2 n-1 -1, 2 n+1 -1}, respectively, to extend the efficiency of reverse converter. The authors in [48] used the multiplication by constant reported in [49] to increase the efficiency.…”

“…The studies [47] and [48] present efficient reverse converters for five moduli set {2 n -1, 2 n , 2 n +1, 2 n+1 +1, 2 n-1 +1} and {2 n -1, 2 k , 2 n +1, 2 n-1 -1, 2 n+1 -1}, respectively, to extend the efficiency of reverse converter. The authors in [48] used the multiplication by constant reported in [49] to increase the efficiency. In this paper, we introduce two fast and area efficient reverse converters for the five-moduli set {2 n +1, 2 n-1 -1, 2 n , 2 n+1 -1, 2 n -1} offering a high-speed arithmetic unit because of its balanced moduli in the form 2 k and 2 k ±1.…”

Classification of Moduli Sets for Residue Number System With Special Diagonal Functions

“…Multiplication of two numbers modulo generally has computational complexity ≈ ( 2 ). If all RNS modules have a very different bit-width, then this will lead to a long idle time of the computational elements for low bit-width modulo while computing for modules of higher bitwidth [13]. This phenomenon is called unbalanced RNS [14].…”