Design of rugged High Voltage high power P-channel silicon MOSFET for plasma applications

Zhang, Jinshu; Sdrulla, Dumitru; Tsang, D. W.; Frey, David; Krausse, G.J.

doi:10.1109/essderc.2008.4681701

Cited by 2 publications

(1 citation statement)

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“…However, the pLDMOS is desirable for high-side applications since it has the advantage of circuit simplification. [9][10][11] Unfortunately, conventional SOI pLDMOS (Con. SOI pLDMOS) at high-side operation suffers from handler wafer biasing, leading to a reduced BV , compared with the nLDMOS at low-side operation.…”

Section: Introductionmentioning

confidence: 99%

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

Zhou¹,

Luo²,

Yang³

et al. 2013

Chinese Phys. B

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A novel low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLD-MOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced) surface field (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV ) but also a significantly reduced R on,sp . The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 µm, and R on,sp decreases from 157 mΩ•cm 2 to 55 mΩ•cm 2 . Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the R on,sp by 34% with almost the same BV .

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Section: Introductionmentioning

confidence: 99%