Design of Self-Refresh bitstream based on FPGA dynamic local reconfiguration

Zhou, Zhimei; Wang, Yübo; Ma, Chaochao; Zhang, Yue; Xu, Hao; Wan, Yong; Xiong, Ke; Chen, Feng

doi:10.1109/aemcse51986.2021.00194

Cited by 1 publication

(2 citation statements)

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“…An alternative option for bit-errors within configuration data exists [ 14 ]. This work utilizes dynamic-reconfiguration, similar to the previously mentioned work.…”

Section: High Performance Networkmentioning

confidence: 99%

“…This review will have importance to future designers who seek to further expand the abilities of reconfigurable hardware in the networking realm, including those interested in Single Event Effect (SEE) correction [ 13 , 14 ] and those interested in applications for partial reconfiguration [ 15 , 16 ]. Future research into FPGA networking capabilitiescan be expedited by reviewing the state-of-the-art works described within this paper.…”

Section: Introductionmentioning

confidence: 99%

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Review of State-of-the-Art FPGA Applications in IoT Networks

Magyari

Chen

2022

Sensors

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Modern networks used for integrating custom Internet of Things (IoT) systems and devices have restrictions and requirements unique to their individual applications. These application specific demands require custom designed hardware to maximize throughput, security and data integrity whilst minimizing latency, power consumption, and form factor. Within this paper, we describe current, state-of-the-art works that utilize FPGAs for IoT network developments. We analyze two categories of works: those that prioritize reducing power consumption, and those that prioritize networking features. Further, we describe how future works can improve upon these designs and therefore improve the efficiency of resource-constrained IoT networks.

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“…An alternative option for bit-errors within configuration data exists [ 14 ]. This work utilizes dynamic-reconfiguration, similar to the previously mentioned work.…”

Section: High Performance Networkmentioning

confidence: 99%