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Two main protocol stacks for gigabit ethernet are currently widely adopted in the data acquisition system for high energy physics experiments. The first method is based on User Datagram Protocol (UDP), which transfer packets before an agreement is provided by the receiving party. However, the second method, called Transmission Control Protocol (TCP), establishes a connection through a process of the three-way handshake. We designed two FPGA projects, based on UDP and TCP respectively, on such a real application as ethernet communication module for ALICE calorimeters. The test of both projects is carried out on the same Xilinx Virtex-6 FPGA board, and data is captured through a professional network protocol analyzer. We analyzed the implementation methods and complexity, the variation patterns of data throughput, and the resource utilization of the two designs. The findings obtained under the same application scenario and test platform not only reveals the variation rule of actual data throughput, but also proved that the TCP would require twice as much FPGA resource for implementation as the UDP.

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As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.