Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations

Sankar, R. S. Prasobh; Asish, L.; Bhuvan, B.

doi:10.1109/apccas47518.2019.8953112

Cited by 3 publications

(2 citation statements)

References 3 publications

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“…The ramp generator employs endpoint error correction to minimize errors at the start and end of the ramp signal, crucial for stable and accurate analog-to-digital conversion. However, the incorporation of advanced error correction techniques and optimizations in the designed ramp generator using standard 180 nm CMOS technology may lead to a more complex circuit design, potentially resulting in increased power consumption and higher implementation costs [4].…”

Section: Introductionmentioning

confidence: 99%

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Malathi,

Malavika

2024

Preprint

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Analog-to-digital converters (ADCs) are essential components in contemporary electronic systems for translating continuous analog signals into digital formats. Emphasizing low power consumption and high conversion efficiency, the project addresses the escalating demand for high-resolution electronic devices. The primary objective is to achieve optimal resolution, crucial for environmental monitoring which demands precision. ADC architecture Ramp ADC is the focal point of the design, implemented within an 18nm FinFET technology framework. The Ramp ADC, with its comparator array and ramp generator, offers simplicity and potential for high-speed applications. The primary objective of this project is to employ a range of design techniques and modifications aimed at reducing power consumption in ADC architecture, all while minimizing the impact on crucial performance metrics, including resolution, speed, and complexity. The comparative analysis focuses on the average power of the ADC, each possessing a resolution of 13 bits. Specifically, modifications applied to the Ramp ADC yield an impressive 47% reduction in average dynamic power, coupled with a notable 28% reduction in static power compared with the existing.

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Section: Introductionmentioning

confidence: 99%

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Malathi,

Malavika

2024

Preprint

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“…In order not to affect the imaging quality of the CIS, the ramp non-uniformity error needs to be controlled within 1/2 LSB. At present, the mainstream ramp generating circuit structures used by CIS include integral ramp generating circuit [4], [5], resistive ramp generating circuit [6], capacitive ramp generating circuit [7], [8], and current steering ramp generating circuit [9], [10]. In [11], an integral ramp generation circuit is used to reduce the gain error of the ramp signal.…”

Section: Introductionmentioning

confidence: 99%

Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors

Xu,

Guo,

Liu

et al. 2024

Chinese J. Elect.

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Aiming at the problem of the non-uniformity of the ramp signal in the super-large array CMOS (complementary metal-oxide semiconductor) image sensors, a ramp uniformity correction method for CMOS image sensors is proposed in this paper. Based on the error storage technique, the ramp non-uniformity error is stored. And the input ramp signal of each column is shifted by level-shifting technique to eliminate the ramp non-uniformity error. Based on the 55 nm-1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixels is 8192 (H) × 8192 (V), and a single pixel size is 10 μm, the correction method proposed in this paper reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The differential non-linearity of the ramp signal is +0.0013/−0.004 LSB and the integral non-linearity is +0.045/−0.021 LSB. The ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. The column fixed-pattern noise is reduced from 1.9% to 0.01%. It provides theoretical support for the design of high-precision CMOS image sensors.

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An Adjustable Ramp Voltage Circuit for a Large Array of Capacitive Loads

Liu,

Zhong,

2023

2022 10th International Symposium on Next-Generation Electronics (ISNE)

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Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations

Cited by 3 publications

References 3 publications

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

High-resolution Environmental Monitoring Adc’s Empowered by 18nm Finfet Technology

Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors

An Adjustable Ramp Voltage Circuit for a Large Array of Capacitive Loads

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