Global Ramp Uniformity Correction Method for Super-Large Array CMOS Image Sensors

Abstract

Aiming at the problem of the non-uniformity of the ramp signal in the super-large array CMOS (complementary metal-oxide semiconductor) image sensors, a ramp uniformity correction method for CMOS image sensors is proposed in this paper. Based on the error storage technique, the ramp non-uniformity error is stored. And the input ramp signal of each column is shifted by level-shifting technique to eliminate the ramp non-uniformity error. Based on the 55 nm-1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixels is 8192 (H) × 8192 (V), and a single pixel size is 10 μm, the correction method proposed in this paper reduces the ramp non-uniformity error from 7.89 mV to 36 μV. The differential non-linearity of the ramp signal is +0.0013/−0.004 LSB and the integral non-linearity is +0.045/−0.021 LSB. The ramp uniformity correction method proposed in this paper reduces the ramp non-uniformity error by 99.54% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. The column fixed-pattern noise is reduced from 1.9% to 0.01%. It provides theoretical support for the design of high-precision CMOS image sensors.