Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

Abstract

A novel method is presented for design of ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed, and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter, positive inverter, and negative inverter and ternary basic gates such as AND, NAND, OR, and NOR gates are designed. Furthermore, half adder circuits are developed, which assists in the development of complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Finally, the performance of the proposed circuits are investigated in terms of delay, power dissipation, and power delay product and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

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