Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates

Balaji, G.; Pandian, S. Chenthur

doi:10.1007/s10586-018-2552-x

Cited by 16 publications

(5 citation statements)

References 6 publications

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“…Concerning the proposed 3-bit TPG, the weight generation is defined as the convolution of the 'm-1' binary additions multiplexed with pseudo primary seeds. Here, the proposed TPG requires only 'm' binary additions and one selection, as shown in equation (4). WE is the estimated weight to be obtained at the ( +1)-th clock cycle, and k denotes the total number of clocks in equation (5).…”

Section: =0mentioning

confidence: 99%

“…The successive weights are generated as an even parity of '0' and an odd parity of '1' concurrently by the Galois operation using equation (1). Additionally, the last term W [∑ −1 =0 ], indicated in equation (4), is assumed to be W[x0] = WA in the TPG. Initially, the weight WA accumulates in the weighted Mux, and later, at the ( + 1)-th iteration, the weight WE is achieved.…”

Section: Figure 5 Flowchart Of the Proposed Weighted Pseudorandom Tpmentioning

confidence: 99%

“…Unlike the current TPG methods [16]- [19], whose hardware complexities are greater than that of the conventional TPG [5], TPG [5] failed to produce efficient weighted patterns. Considerably, the weighted TPG is proposed to reduce the gate counts by applying the Galois operation linear property, according to (4) and (5). The 32-bit proposed TPG occupies an area of 4263 µm 2 , which is approximately 51% less than that of TPG [16].…”

Section: Operation Of Proposed Weighted Pseudorandom Tpg With Simumentioning

confidence: 99%

“…The TPG linear function is accomplished according to the output feedback signal and the input seed bits [3]. Its linear functionalities are used in many applications such as aircraft systems, cockpit systems, medical systems, audio and video systems, and power generation and distribution systems [4]. A TPG consists of deterministic, exhaustive, pseudorandom, pseudorandom-weighted, and mixed-mode outputs [6].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

2021

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A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra 0.13 µm process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs. INDEX TERMS built-in self-test (BIST), circuit under test (CUT), test-pattern generator (TPG).

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Section: =0mentioning

confidence: 99%

Section: Figure 5 Flowchart Of the Proposed Weighted Pseudorandom Tpmentioning

confidence: 99%

Section: Operation Of Proposed Weighted Pseudorandom Tpg With Simumentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

2021

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“…The MBIST controller usually works on test algorithms for finding defects and their types in embedded memories [11,12]. Testing the embedded memories by the test-pattern generator (TPG), using a scan chain method, is proposed in the research [13,14] to target less power consumption. Test time and test power are analyzed by the proposed scan chain architecture and LFSR.…”

Section: Introductionmentioning

confidence: 99%

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer

Ahmed

2021

Micromachines

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The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

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Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization

Thangam,

Manjith

2024

J Electron Test

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Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates

Cited by 16 publications

References 6 publications

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization

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