Design of the Power6 Microprocessor

Friedrich, Joshua; McCredie, B.D.; James, N.; Huott, B.; Curran, Brian; Fluhr, Eric; Mittal, Gaurav; Chan, Eric Y.; Chan, Yiu-Hing; Plass, D.; Chu, Sam; Le, H. Q.; Clark, Lawrence T.; Ripley, J.; Taylor, Scott A.; DiLullo, Jack; Lanzerotti, Mary

doi:10.1109/isscc.2007.373605

Cited by 81 publications

(26 citation statements)

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“…Though their architecture improves yield significantly, it is not suitable for severe process variation environments because the reduced number of available cache lines leads to large performance overhead. The IBM Cell [24] and Power6 [9] processor both use increased array supply voltage to improve stability and read performance. However, their technique exercises a much coarser control granularity and they raise SRAM cell supply while we proposed to have fine-grain wordline voltage boosting.…”

Section: Related Workmentioning

confidence: 99%

Selective wordline voltage boosting for caches to manage yield under process variations

Pan

Kong

Özdemir

et al. 2009

Proceedings of the 46th Annual Design Automation Conference

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One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

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Section: Related Workmentioning

confidence: 99%

Selective wordline voltage boosting for caches to manage yield under process variations

Pan

Kong

Özdemir

et al. 2009

Proceedings of the 46th Annual Design Automation Conference

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“…Multithreading is using a different programming approach [21] that exploits concurrency offered by processors with multicores [2][3][4][5][6][7]. It needs only a multicore processor, which is readily available today and cheaper than a network of processors.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

“…The switch to parallel microprocessors represents a cornerstone in the history of computing [1], and the current trend is to continuously increase the number of cores per chip [2][3][4][5][6][7]. Despite the fact that parallel computing has been discussed for a long time [8,9], it is still a challenging task to find the most appropriate parallelization technique and application transformation that would maximize the benefit of parallelism.…”

Section: Introductionmentioning

confidence: 99%

Speeding Up FPGA Placement via Partitioning and Multithreading

Ababei

2009

International Journal of Reconfigurable Computing

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One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

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“…Our baseline is a multithreaded, multi-core architecture (referred to sometimes as chip multithreading [12]). Several examples of this architecture already exist in industry [3,5,8,6]. …”

Section: The Baseline Multithreaded Multicore Architecturementioning

confidence: 99%

The shared-thread multiprocessor

Brown

Tullsen

2008

Proceedings of the 22nd Annual International Conference on Supercomputing

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This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor; specifically, it enables distinct cores on a chip multiprocessor to share thread state. This shared thread state allows the system to schedule threads from a shared pool onto individual cores, allowing for rapid movement of threads between cores.This paper demonstrates and evaluates three benefits of this architecture: (1) By providing more thread state storage than available in the cores themselves, the architecture enjoys the ILP benefits of many threads, but carries the in-core complexity of supporting just a few. (2) Threads can move between cores fast enough to hide long-latency events such as memory accesses. This enables very-shortterm load balancing in response to such events. (3) The system can redistribute threads to maximize symbiotic behavior and balance load much more often than traditional operating system thread scheduling and context switching.

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Design of the Power6 Microprocessor

Cited by 81 publications

References 1 publication

Selective wordline voltage boosting for caches to manage yield under process variations

Selective wordline voltage boosting for caches to manage yield under process variations

Speeding Up FPGA Placement via Partitioning and Multithreading

The shared-thread multiprocessor

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