The shared-thread multiprocessor

Abstract

This paper describes initial results for an architecture called the Shared-Thread Multiprocessor (STMP). The STMP combines features of a multithreaded processor and a chip multiprocessor; specifically, it enables distinct cores on a chip multiprocessor to share thread state. This shared thread state allows the system to schedule threads from a shared pool onto individual cores, allowing for rapid movement of threads between cores.This paper demonstrates and evaluates three benefits of this architecture: (1) By providing more thread state storage than available in the cores themselves, the architecture enjoys the ILP benefits of many threads, but carries the in-core complexity of supporting just a few. (2) Threads can move between cores fast enough to hide long-latency events such as memory accesses. This enables very-shortterm load balancing in response to such events. (3) The system can redistribute threads to maximize symbiotic behavior and balance load much more often than traditional operating system thread scheduling and context switching.

Fast thread migration via cache working set prediction

“…Previous work [3,38] describes support mechanisms for migrating register state in order to decrease the latency of thread activation and deactivation; however, performance subsequent to migration still suffers due to cold-cache effects. Our work is complimentary; we specifically address the post-migration cache misses which limit the gains of those techniques.…”

“…The cores of our CMP feature hardware support for thread activation and deactivation, as found in prior studies of thread scheduling [3,38]. While those works used hardware support to implement scheduling and time-sharing policies, we use it simply for adding and removing threads from cores.…”

An Attempt to Improve the Processor Performance by Proper Memory Management for Branch Handling

“…Pseudo-parallelism share the some technical issues in common, related to the need for synchronisation between running programs. Figure 1 is somewhat detailed view of the running of the four programs-labelled P1, P2, P3, and P4-in multiprogramming mode [5]. The top part of the figure, all the four programs seems to be running in parallel.…”

Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality

“…If there is data in cache on the user processor that must be accessed by the OS core, it must be transferred to the OS core (automatically handled by the coherence mechanism). The aggressive scheme is based on the technique proposed by Brown and Tullsen [9] and is assumed to incur a 100 cycle migration latency. They advocate hardware support for book-keeping and thread scheduling (normally done in software by an OS or virtual machine).…”

“…The work by Brown and Tullsen [9], for example, attempts to design a low-latency process migration mechanism that is an important technology for OS off-load. Similarly, in this paper we assume that OS off-load is a promising approach and we attempt to resolve another component of OS off-load that may be essential for its eventual success, viz, the decision-making process that determines which operations should be off-loaded.…”