Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures

This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4 GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5 V. This mixer is simulated and verified in 0.13 μm standard CMOS technology. The result shows a conversion gain (CG) of 11.84 dB, 1 dB compression point (P 1 dB ) at −14.36 dBm, third-order intercept point (IIP3) of −5 dBm and a noise figure (NF) of 15 dB and with a power consumption of 930 μW. Keywords: mixer, ultra-low voltage, CMOS, ZigBee, current bleeding Classification: Integrated circuits References[1] T. Song, H.-S. Oh, and S. Hong, "A low-power 2.4GHz current-reused receiver front-end and frequency source for wireless sensor network," IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1012-1022

Section: Proposed Ultra-low Voltage Mixer Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of ultra-low voltage 0.5V CMOS current bleeding mixer

Tan

Sidek

Ramiah

et al. 2012

“…Source inductive degeneration has been employed widely in recent years [1,2,3,4]. Although this technique is suitable for LNA input matching in a narrow frequency band, it degrades the power gain of the LNA significantly, and hence the power gain decrement should be compensated with greater DC current.…”

Section: Introductionmentioning

confidence: 99%

A new g<sub>m</sub>-boosting current reuse CMOS folded cascode LNA

Kargaran¹,

Mafinejad

Mafinezhad³

et al. 2013

In this paper, a new gain enhancement technique which is recommended for folded cascode LNA structures at low voltage and low power applications is presented. In order to increase power gain, a new modified version of g m -boosting technique is employed which increases the power gain while consuming no extra power. The new topology shares its DC current at the folded stage in order to reduce power dissipation associated with the g m -boosting technique. The proposed technique reduces power dissipation almost 27%, additionally; other parameters such as power gain and noise figure have been slightly improved. In the proposed LNA, power gain and noise figure are15 dB and 3.2 dB respectively. It consumes 1.3 mW under 0.6 supply voltage.

“…Insufficient voltage headroom results in some circuit topologies unable to satisfy the required specifications or even unable to operate. Hence, research for low-voltage circuit topologies is important [1,2,3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

Design of a low-voltage CMOS mixer based on variable load technique

Wei

Dai

Wang

et al. 2010

A CMOS active mixer based on variable load technique which can operate at 1.0 V supply voltage is proposed and its operation principle is presented. The proposed mixer controls the load impedance according to the LO signal. It has only two stacked transistors at each branch, which is suitable for low-voltage applications. The mixer was designed in 0.18-μm CMOS process and measured in 2.4-GHz ISM band. With a 2.440 GHz RF input signal and a 2.442 GHz LO signal (4 dBm), the conversion gain is 5.3 dB, the input-referred third-order intercept point is 4.6 dBm, the input-referred 1-dB compression point is −7.4 dBm, and the single-sideband noise figure is 21.7 dB. Current consumption is 3.5 mA at 1.0 V supply. Keywords: CMOS active mixer, variable load technique, low-voltage Classification: Integrated circuits References