Design of vedic multiplier using adiabatic logic

Abstract

A multiplier is a vital element in many arithmetic and logical units, digital signal processing and communication system. Therefore speed, area and power consumptions are the critical parameters for the designing of multiplier circuits. This paper presents a comparative study of binary Vedic multiplier using CMOS, PFAL and ECRL. The design is based on ancient Indian Vedic mathematics and the low power charge recovery logic. In Vedic multiplication, generation of partial sums and products is performed in single step so this along with adiabatic approach helps in realizing the high speed and low power operation of the binary Vedic multiplier design. The designs are simulated on Cadence Virtuoso Tool using UMC 180 nm CMOS technology. Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

“…Adiabatic logic is utilized to minimize power consumption of Vedic multiplier and its performance is estimated by comparing it with traditional MOS design. Vedic multiplier with adiabatic logic consumes less power than Vedic multiplier without adiabatic logic analysed in [6], [7].…”

ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

“…Nearly similar work was also carried out by Sharma and Goyal [31] most recently only with a difference that actual work of Pohokar [30] was implemented in FPGA in 2015 and same work was also published by Sharma and Goyal [31] in H-Spice in 2016. Singh and Sasamal [32] have presented a study where binary Vedic multiplier is implemented over cadence tool using adiabatic logic. Usage of another Vedic sutra called as Calana Kalanabhyam was seen in the work of Verma et al [33] where the authors have used it alongside with FPGA to make energy-efficient sutra.…”