Design of voltage-scalable meta-functions for approximate computing

Mohapatra, D.; Chippa, Vinay K.; Raghunathan, Anand; Roy, Kaushik

doi:10.1109/date.2011.5763154

Cited by 175 publications

(62 citation statements)

References 8 publications

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“…Compared to an exponent subtractor, the mantissa adder offers a larger design space for inexact design, because the number of bits in the mantissa adder is significantly larger than the exponent subtractor. As shown in Table 1, the number of mantissa bits is larger than the number of exponent bits [7] .For the IEEE single precision format, the exponent subtractor is an 8-bit adder, while the mantissa adder is a 25-bit adder (for two24-bit significances). Furthermore, the inexact design in the mantissa adder has a lower impact on the error than its exponent counterpart in the lower data range, because the mantissa part is less significant than the exponent part.…”

Section: Mantissa Addermentioning

confidence: 99%

“…An inexact fixed-point adder has been extensively studied and can be used in the exponent adder inexact adders such as lower-part-OR adders (LOA) [3], approximate mirror adders [4], approximate XOR/XNORbased adders, and equal segmentation adders [6], [7] can be found in the literature [1,2,3]. For a fast FP adder, a revised LOA adder is used, because it significantly reduces the critical path by ignoring the lower carry bits.…”

Section: Exponent Subtractormentioning

confidence: 99%

“…Inexact chips are smaller, faster and consume less energy. For inexact computing, fixed point arithmetic circuits have been already studied [2], [3], [4], [5], [6], [7], [8] as mentioned in the literature floating-point (FP) circuits consumes significantly more power due to its more complexity they have not been recommended for inexact computing. In computationally intensive applications FP format offers a large range dynamically.…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Low Power Inexact Floating Point Adder

Pedraj¹,

Kumar²

2017

IJCA

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Floating-point applications are a growing trend in the FPGA community. In nanoscale integrated circuits design as the demand for mobile computing & higher integration density is increasing power is becoming a very important constraint. Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. For some applications where error is in tolerable range an inexact circuit offers reduction in both static and dynamic power .In this paper, an inexact floating-point adder is designed by approximating exponent sub tractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. It is then observed that it greatly reduced the power consumption and hence increased the reliability. KeywordsFloating-point adders, low power, high dynamic range image, inexact circuits, error analysis.

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Section: Mantissa Addermentioning

confidence: 99%

Section: Exponent Subtractormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Low Power Inexact Floating Point Adder

Pedraj¹,

Kumar²

2017

IJCA

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“…The approximate adders could be broadly categorized into two types. The first type is due to the impact of timinginduced errors when a n bit ripple carry adder (RCA) is divided into several k-bit sub-adders (k < n), e.g., [2,3,4,5]. These designs cut the carry propagation chain to induce some errors to approximately calculate the results.…”

Section: Introductionmentioning

confidence: 99%

An analytical framework for error modeling of approximate adders

Yang

Xing

et al. 2016

IEICE Electron. Express

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Approximate computing has drawn recent attention as it can reduce power without significantly sacrificing the output quality for arithmetic operations in error-resilient applications. However, the error characteristics evaluation often depends on time consuming random simulation and estimation. In this paper, a formal framework of evaluating approximate adders is proposed based on a theoretical model. The proposed framework can accurately measure mean squared error (MSE) and mean absolute error (MAE) without using functional simulations. An approach has been adopted to estimate the final PSNR value in terms of MSE and MAE for DCT-IDCT image compression system. Experimental results have validated the accuracy and usefulness of the framework. Keywords: approximate computing, error modeling and analysis, approximate adder, squared error, absolute error Classification: Integrated circuits

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“…For example, in audio and image processing or in wireless communication, it might be desirable to get better performance (faster, smaller, less powerhungry systems) at expenses of some quality degradation. Recently, a few papers have addressed this issue of designing imprecise hardware to save power [1], [2], [3], [4]. In this work, we introduce a systematic way of having imprecise arithmetic operations for the two most common operations: addition and multiplication.…”

Section: Introductionmentioning

confidence: 99%

Imprecise arithmetic for low power image processing

Albicocco

Cardarilli

Nannarelli

et al. 2012

2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

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Abstract-Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, addition and multiplication, in an imprecise manner by simplifying the hardware implementation. With the proposed "sloppy" operations, we obtain a reduction in delay, area and power dissipation, and the error introduced is still acceptable for applications such as image processing.

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Design of voltage-scalable meta-functions for approximate computing

Cited by 175 publications

References 8 publications

Design and Implementation of Low Power Inexact Floating Point Adder

Design and Implementation of Low Power Inexact Floating Point Adder

An analytical framework for error modeling of approximate adders

Imprecise arithmetic for low power image processing

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